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33486A Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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33486A Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
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3 / 30 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 3 33486A TERMINAL CONNECTIONS TERMINAL CONNECTIONS Figure 3. 33486A Terminal Locations Table 1. TERMINAL DEFINITIONS Terminal Terminal Name Formal Name Definition 1 GND Ground This is the ground terminal of the device. 2 Cur R Load Current Sense The Current Sense terminal delivers a ratio amount of the sum of the high-side currents. 3 18 IN1 IN2 Input Channel 1 Input Channel 2 These are the device input terminals that directly control their associated outputs. Each input terminal has an internal active pull-down so that the input terminal will not float if disconnected. 4 17 GLS1 GLS2 Gate Low-Side 1 Gate Low-Side 2 Each terminal must be connected to one gate of an external low-side MOSFET. 5–8 OUT1 Output Channel 1 Terminals 5, 6, 7, and 8 are the source of the Output Channel 1 15 m Ω high-side MOSFET1. 9–12 NC No Connect These terminals are not used. 13–16 OUT2 Output Channel 2 Terminals 13, 14, 15, and 16 are the source of the Output Channel 2 15 m Ω high-side MOSFET2. 19 ST Status for Both Channels The status output goes low when a fault mode is detected. It is an open drain with an internal clamp at 6.0 V. An external pull-up resistor connected to VDD (5.0 V) is needed. 20 WAKE Wake This logic input enables control of the device. (Wake logic LOW = Sleep Mode, Wake logic HIGH = full operation.) The WAKE terminal has a pull- down resistor. TAB VBAT Supply Voltage The backside TAB is connected to the power supply of the 33486A. WAKE GND ST IN2 GLS2 OUT2 OUT2 OUT2 OUT2 NC NC Cur R OUT1 OUT1 OUT1 OUT1 NC NC IN1 GLS1 1 2 3 4 5 6 7 8 9 10 20 19 16 15 14 13 12 11 18 17 VBAT VBAT |
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