9

Analog Devices

Skip ROM [CCh]

This command can save time in a single drop bus system by allowing the bus controller to access the

clock functions without providing the 64-bit ROM code. If more than one peripheral is present on the bus

and, for example, a read command is issued following the Skip ROM command, data collision will occur

on the bus as multiple peripherals transmit simultaneously (open drain pull-downs will produce a wired-

AND result).

1-Wire Signaling

The DS1904 requires strict protocols to ensure data integrity. The protocol consists of four types of

signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, and Read

Data. Except for the presence pulse, the bus controller initiates all of these signals.

The initialization sequence required to begin any communication with the DS1904 is shown in Figure 8.

A reset pulse followed by a presence pulse indicates the DS1904 is ready to send or receive data. The

bus controller transmits (Tx) a reset pulse (tRSTL, minimum 480μs). The bus peripheral then releases the

line and goes into receive mode (Rx). The 1-Wire bus is pulled to a high state via the pull-up resistor.

After detecting the rising edge on the data line, the DS1904 waits (tPDH, 15-60μs) and then transmits the

presence pulse (tPDL, 60-240μs).

Initialization Procedure “Reset and Presence Pulses” Figure 8

Read/Write Time Slots

The definitions of write and read time slots are illustrated in Figure 9. The controller initiates all time slots

by driving the data line low. The falling edge of the data line synchronizes the DS1904 to the controller

by triggering an internal delay circuit. During write time slots, the delay circuit determines when the

DS1904 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit

determines how long the DS1904 will hold the data line low. If the data bit is a “1”, the DS1904 will not

hold the data line low at all.

VPULLUPMIN

CONTROLLER RX “PRESENCE PULSE”

VPULLUP

VIHMIN

VILMAX

0V

CONTROLLER TX

“RESET PULSE”

tRSTL

tRSTH

480µs < tRSTL < ∞*

480µs < tRSTH < ∞**

15µs < tPDH < 60µs

60µs < tPDL < 240µs

CONTROLLER

DS1904

RESISTOR

tPDH

tR

tPDL

* IN ORDER NOT TO MASK INTERRUPT SIGNALING BY OTHER DEVICES ON THE 1-Wire BUS, tRSTL + tR SHOULD

ALWAYS BE LESS THAN 960µs.

** INCLUDES RECOVERY TIME