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TUSB6020

USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER

SCPS170C – JANUARY 2007 – REVISED JULY 2007

• USB On-the-Go (OTG) Controller Core

–

Use 19.200-MHz, 24.000-MHz, or

48.000-MHz Reference Clock Input as a

–

Use Mentor Graphics USB 2.0 OTG Core

Crystal or External Clock Driver

–

Dual-Role Controller Can Operate Either as

–

At-Speed Built-In Self Test (BIST) With

a Function Controller for a USB Peripheral

Internal Asynchronous Capability Through

or as the Host/Peripheral in Point-to-Point

Loopback

or Multi-Point Communications With Other

USB Functions

–

On-Chip Integrated Accurate 45-

Ω

High-Speed Termination, 1.5-k

Ω Pullup,

–

Compliant With the USB 2.0 Standard for

and 15-k

Ω Pulldown Resistors

High-Speed (480-Mbps) Functions and

With the OTG Supplement to the USB 2.0

–

On-Chip Phase-Locked Loop (PLL) to

Specification

Reduce Noise on the High-Speed Clocks

–

Supports OTG Communications With One

–

Active Power Consumption Less Than

or More High-, Full-, or Low-Speed Devices

100 mW

–

Supports Session Request Protocol (SRP)

• VLYNQ 2.0 Interface to External Host

and Host Negotiation Protocol (HNP)

Controller

–

Supports Suspend-and-Resume Signaling

–

High-Speed (150-MHz) Point-to-Point Serial

Interface for Direct Connection to Other

–

Configurable for up to 15 Transmit

VLYNQ Interface

Endpoints and up to 15 Receive Endpoints

–

Supports 4X RX and 4X TX Lines

–

Configurable FIFOs, Including the Option

of Dynamic FIFO Sizing

–

Memory-Mapped Master/Slave

–

16k-Byte RAM for USB Endpoint FIFO

–

Hardware Flow Control Internal Loopback

Shared by USB In/Out Endpoints

Mode

–

Support for External Direct Memory

–

Multichannel DMA Controller

Access (DMA) to FIFOs

–

Integrated List Processor Capable of

–

Soft Connect/Disconnect Option

Parsing Communications Port

Programming Interface (CPPI)

–

Performs All Transaction Scheduling in

3.0-Compliant Buffer Descriptors

Hardware

• System Control Module

• Integrated USB 2.0 OTG PHY

–

Controls Clock and Reset Generation and

–

Fully Compliant With USB 2.0 Standard

Distribution

and USB 2.0 Transceiver Macrocell

Interface (UTMI) Revision 1.05

–

Controls and Observes Device Power

States

–

Optimized One-Port Operation at Low

Speed (1.5 Mbps), Full Speed (12 Mbps),

–

Controls Test and Debug Modes

and High Speed (480 Mbps)

–

Supports External Power Management

–

Support for External Charge Pump

• V

–

Supports UTMI+3 Level 3 (Host and OTG

–

Supports Two VBUSP Master and Three

Devices, High/Full/Low Speed and

VBUSP Slave Interfaces

Preamble Packet)

• High-Performance 80-Pin

–

Protection Circuitry to Withstand Possible

MicroStar BGA™/MicroStar Junior™

VBUS Short

ZQE Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar BGA, MicroStar Junior, MicroStar BGA are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the

Copyright © 2007, Texas Instruments Incorporated

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.