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TUSB6020

USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER

SCPS170C – JANUARY 2007 – REVISED JULY 2007

TERMINAL FUNCTIONS

TERMINAL

RESET

TYPE

I/O

DESCRIPTION

STATE

NAME

NO.

1.5V_SWEN

G2

LVCMOS

O

0

Switch enable for 1.5-V LDO for VBAT/VBUS switch

3.3V_SWEN

G3

LVCMOS

O

0

Switch enable for 3.3-V CP for VBAT/VBUS switch

LVCMOS

CLKIN

A5

I

In

System clock in. Connect directly to ground if not used.

failsafe

CPEN

H2

LVCMOS

O

0

5-V charge pump enable

DM

E2

USB

I/O

–

USB differential pair

DP

D1

LVCMOS

I/O

–

USB differential pair

A8, B7,

B8, B9,

C6, C7,

GND

–

–

–

Ground

C8, D6,

D8, E7,

G4, J5

GPIO0

H4

LVCMOS

I/O

In with pullup

GPIO 0

GPIO1

D5

LVCMOS

I/O

In with pullup

GPIO 1

GPIO2

B6

LVCMOS

I/O

In with pullup

GPIO 2

GPIO3

E6

LVCMOS

I/O

In with pullup

GPIO 3

GPIO4

C4

LVCMOS

I/O

In with pullup

GPIO 4

GPIO5

C9

LVCMOS

I

In with pullup

GPIO 5

GPIO 6. Input clock source select at reset. GPIO6 = HIGH,

GPIO6

F5

LVCMOS

I/O

In with pullup

CLKIN is reference clock. GPIO6 = LOW, XI is reference

clock.

GPIO7

B2

LVCMOS

I/O

In with pullup

GPIO 7. Must be pulled low for proper operation

Indicates default master for OTG. For more information, see

ID

F2

USB

I

–

On-the-Go Supplement to the USB Specification, Revision 1.2

High-precision external resistor used for calibration.

R1

C2

Bias

I

–

(R1 value: 10 K

±1%)

RSTn

H1

LVCMOS

I

In with pullup

Reset active low

G5, H5,

RSVD

–

–

–

Reserved

J4, F6

SLEEP

H3

LVCMOS

O

0

OTG sleep

Test mode. Under normal operation, this signal should be tied

TEST

D4

LVCMOS

I

–

directly to GND.

Charged, discharged, and monitored for OTG host negotiation

VBUS

F3

USB

I

–

protocol and session request protocol. External charge pump

provides up to 100 mA.

A1, A9,

VDD15

B3, C5,

Supply

–

–

Digital core power supply, 1.5 V

D7, J3

A7, B5,

VDD18

Supply

–

–

I/O power supply, 1.8 V

E8, J1

VDDA1P5

E3

Supply

–

–

1.5-V analog supply

VDDA3P3

C1

Supply

–

–

3.3-V analog supply

VDDCM1P5

D2

Supply

–

–

1.5-V PLL supply

VDDD1P5

F1

Supply

–

–

1.5-V digital supply

F8, G6,

VDDS3P3

Supply

–

–

VLYNQ supply, 3.3 V

J9

VLYNQ_CLK

F9

LVCMOS

I

In with pullup

VLYNQ clock

LVCMOS

VLYNQ_CRUN

E9

I/O

In with pullup

VLYNQ clock run

open drain

VLYNQ_RXD0

H7

LVCMOS

I

In with pullup

VLYNQ receive data bit 0

VLYNQ_RXD1

J7

LVCMOS

I

In with pullup

VLYNQ receive data bit 1

3

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