TMDS442 datasheet(30/45 Pages) TI

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TMDS442 Read Phase 2:

Supply Voltage

TMDS Inputs

TMDS442

SLLS757A – AUGUST 2006 – REVISED MARCH 2007

Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND.

STEP 3

I2C Acknowledge (Slave)

STEP 4

I2C Read Sink Port Address (Master)

Addr

Where Addr is determined by the values shown in Table 2.

STEP 5

I2C Acknowledge (Slave)

STEP 6

I2C Stop (Master)

STEP 7

I2C Start (Master)

STEP 8

I2C General Address (Master)

Where X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND.

STEP 9

I2C Acknowledge (Slave)

STEP 10

I2C Read Data (Slave)

Data

Where Data is determined by the logic values contained in the Sink Port Register.

STEP 11

I2C Not-Acknowledge (Master)

STEP 12

I2C Stop (Master)

All VCC pins can be tied to a single 3.3-V power source. A 0.01-µF capacitor is connected from each VCC pin

directly to ground to filter supply noise.

Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each

input channel contains an 8-dB equalization circuit to compensate for cable losses. The voltage at the TMDS

input pins must be limited per the absolute maximum ratings. An unused input should not be connected to

ground as this would result in excessive current flow damaging the device. TMDS input pins do not incorporate

failsafe circuits. An unused input channel can be externally biased to prevent output oscillation. The

complementary input pin is recommended to be grounded through a 1-k

Ω resistor and the other pin left open.

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