MAX8745 datasheet(33/36 Pages) MAXIM

33 / 36 page

High-Efficiency, Quad Output, Main Power-

Supply Controllers for Notebook Computers

______________________________________________________________________________________

The output capacitor and the load resistance create the

dominant pole in the system. However, the internal ampli-

fier delay, the pass transistor’s input capacitance, and the

stray capacitance at the feedback node create additional

poles in the system, and the output capacitor’s ESR gen-

erates a zero. For proper operation, use the following

steps to ensure the linear-regulator stability:

1) First, calculate the dominant pole set by the linear

regulator’s output capacitor and the load resistor:

where COUTA is the output capacitance of the aux-

iliary LDO and RLOAD is the load resistance corre-

sponding to the maximum load current. The unity-

gain crossover of the linear regulator is:

fCROSSOVER = AV(LDO)fPOLE(LDO)

2) The pole caused by the internal amplifier delay is at

approximately 1MHz:

fPOLE(AMP)

≈ 1MHz

3) Next, calculate the pole set by the transistor’s input

capacitance, the transistor’s input resistance, and

the base-to-emitter pullup resistor. Since the tran-

sistor’s input resistance (hFE/gm) is typically much

greater than the base-to-emitter pullup resistance,

the pole can be determined from the simplified

equation:

where gm is the transconductance of the pass tran-

sistor, and fT is the transition frequency. Both para-

meters can be found in the transistor’s data sheet.

Therefore, the equation can be further reduced to:

4) Next, calculate the pole set by the linear regulator’s

feedback resistance and the capacitance between

FBA and ground (approximately 5pF including

stray capacitance):

5) Next, calculate the zero caused by the output

capacitor’s ESR:

where RESR is the equivalent series resistance of

COUTA.

6) To ensure stability, choose COUTA large enough so

that the crossover occurs well before the poles and

zero calculated in steps 2 through 5. The poles in

steps 3 and 4 generally occur at several MHz, and

using ceramic output capacitors ensures the ESR

zero occurs at several MHz as well. Placing the

crossover frequency below 500kHz is typically suf-

ficient to avoid the amplifier delay pole and gener-

ally works well, unless unusual component

selection or extra capacitance moves the other

poles or zero below 1MHz.

A capacitor connected between the linear regula-

tor’s output and the feedback node can improve

the transient response and reduce the noise cou-

pled into the feedback loop.

If a low-dropout solution is required, an external p-

channel MOSFET pass transistor could be used.

However, a pMOS-based linear regulator requires

higher output capacitance to stabilize the loop. The

high gate capacitance of the p-channel MOSFET

lowers the fPOLE(CIN) and can cause instability. A

large output capacitance must be used to reduce

the unity-gain bandwidth and ensure that the pole

is well above the unity-gain crossover frequency.

Applications Information

Duty-Cycle Limits

Minimum Input Voltage

The minimum input operating voltage (dropout voltage)

is restricted by the maximum duty-cycle specification

(see the Electrical Characteristics table). For the best

dropout performance, use the slowest switching fre-

quency setting (200kHz, FSEL = GND). However, keep

in mind that the transient performance gets worse as

the step-down regulators approach the dropout volt-

age, so bulk output capacitance must be added (see

the voltage sag and soar equations in the SMPS Design

Procedure and Transient Response sections). The

absolute point of dropout occurs when the inductor cur-

rent ramps down during the off-time (

ΔIDOWN) as much

as it ramps up during the on-time (

ΔIUP). This results in

a minimum operating voltage defined by the following

equation:

ZERO ESR

OUTA ESR

()

POLE FBA

FBA

()

(||

)

POLE CIN

()

≈

POLE CIN

IN IN

()

≈

POLE LDO

OUTA LOAD

()

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