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AM3359 Datasheet(PDF) 79 Page - Texas Instruments

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Part # AM3359
Description  AM335x Sitara™ Processors
PDF  256 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM3359 Datasheet(HTML) 79 Page - Texas Instruments

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com
SPRS717L – OCTOBER 2011 – REVISED MARCH 2020
Submit Documentation Feedback
Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
Specifications
Copyright © 2011–2020, Texas Instruments Incorporated
5
Specifications
5.1
Absolute Maximum Ratings
over junction temperature range (unless otherwise noted)
(1)(2)
MIN
MAX
UNIT
VDD_MPU(3)
Supply voltage for the MPU core domain
–0.5
1.5
V
VDD_CORE
Supply voltage for the core domain
–0.5
1.5
V
CAP_VDD_RTC(4)
Supply voltage for the RTC core domain
–0.5
1.5
V
VPP(5)
Supply voltage for the FUSE ROM domain
–0.5
2.2
V
VDDS_RTC
Supply voltage for the RTC domain
–0.5
2.1
V
VDDS_OSC
Supply voltage for the System oscillator
–0.5
2.1
V
VDDS_SRAM_CORE_BG
Supply voltage for the Core SRAM LDOs
–0.5
2.1
V
VDDS_SRAM_MPU_BB
Supply voltage for the MPU SRAM LDOs
–0.5
2.1
V
VDDS_PLL_DDR
Supply voltage for the DPLL DDR
–0.5
2.1
V
VDDS_PLL_CORE_LCD
Supply voltage for the DPLL Core and LCD
–0.5
2.1
V
VDDS_PLL_MPU
Supply voltage for the DPLL MPU
–0.5
2.1
V
VDDS_DDR
Supply voltage for the DDR I/O domain
–0.5
2.1
V
VDDS
Supply voltage for all dual-voltage I/O domains
–0.5
2.1
V
VDDA1P8V_USB0
Supply voltage for USBPHY
–0.5
2.1
V
VDDA1P8V_USB1(6)
Supply voltage for USBPHY
–0.5
2.1
V
VDDA_ADC
Supply voltage for ADC
–0.5
2.1
V
VDDSHV1
Supply voltage for the dual-voltage I/O domain
–0.5
3.8
V
VDDSHV2(6)
Supply voltage for the dual-voltage I/O domain
–0.5
3.8
V
VDDSHV3(6)
Supply voltage for the dual-voltage I/O domain
–0.5
3.8
V
VDDSHV4
Supply voltage for the dual-voltage I/O domain
–0.5
3.8
V
VDDSHV5
Supply voltage for the dual-voltage I/O domain
–0.5
3.8
V
VDDSHV6
Supply voltage for the dual-voltage I/O domain
–0.5
3.8
V
VDDA3P3V_USB0
Supply voltage for USBPHY
–0.5
4
V
VDDA3P3V_USB1(6)
Supply voltage for USBPHY
–0.5
4
V
USB0_VBUS(7)
Supply voltage for USB VBUS comparator input
–0.5
5.25
V
USB1_VBUS(6)(7)
Supply voltage for USB VBUS comparator input
–0.5
5.25
V
DDR_VREF
Supply voltage for the DDR SSTL and HSTL reference voltage
–0.3
1.1
V
Steady state max voltage
at all I/O pins(8)
–0.5 V to I/O supply voltage + 0.3 V
USB0_ID(9)
Steady state maximum voltage for the USB ID input
–0.5
2.1
V
USB1_ID(6)(9)
Steady state maximum voltage for the USB ID input
–0.5
2.1
V
Transient overshoot and
undershoot specification at
I/O terminal
25% of corresponding I/O supply
voltage for up to 30% of signal
period
Latch-up performance(10)
Class II (105°C)
45
mA
Class II (125°C)
1.8-V mode
–100
100
mA
3.3-V mode; applies to all I/O pins except those
included in latch-up pin groups A(12), B(13), and C(14)
–100
100
3.3-V mode; applies to latch-up pin group A(12)
–35
100
3.3-V mode; applies to latch-up pin group B(13)
–45
75
3.3-V mode; applies to latch-up pin group C(14)
–100
70
Storage temperature,
Tstg
(11)
–55
155
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated VSS or VSSA_x.
(3) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE on the ZCE package.
(4) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.



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