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AM3359 Datasheet(PDF) 80 Page - Texas Instruments |
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AM3359 Datasheet(HTML) 80 Page - Texas Instruments |
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80 / 256 page ![]() 80 AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 SPRS717L – OCTOBER 2011 – REVISED MARCH 2020 www.ti.com Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Specifications Copyright © 2011–2020, Texas Instruments Incorporated Absolute Maximum Ratings (continued) over junction temperature range (unless otherwise noted)(1)(2) (5) During functional operation, this pin is a no connect. (6) Not available on the ZCE package. (7) This terminal is connected to a fail-safe I/O and does not have a dependence on any I/O supply voltage. (8) This parameter applies to all I/O terminals which are not fail-safe and the requirement applies to all values of I/O supply voltage. For example, if the voltage applied to a specific I/O supply is 0 volts the valid input voltage range for any I/O powered by that supply will be –0.5 to +0.3 V. Apply special attention anytime peripheral devices are not powered from the same power sources used to power the respective I/O supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences. (9) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the voltage to determine if the terminal is connected to VSSA_USB with a resistance less than 10 Ω or greater than 100 kΩ. The terminal should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any external voltage source. (10) Based on JEDEC JESD78D [IC Latch-Up Test]. (11) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning to ambient room temperature before usage. (12) Latch-up pin group A: V7, R8, T8, U8, V8, R9, T9, U10, T10, T11, U12, T12, R12, V13, U13, R13, V14, U14, T14, R14, V15, U15, T15, V16, U16, T16, V17, U17, U18, U9, V9, T13, V12, V4 (13) Latch-up pin group B: R1, R2, R3, R4, T1, T2, T3, V2, V3 (14) Latch-up pin group C: T4, U1, U2, U3, U4, V5, F17, F18, G15, G16, G17, G18, H16, H17, J15, J16, J17, J18, K15, K16, K17, K18, L18, L17, L16, L15, M16, H18, M17, M18 Fail-safe I/O terminals are designed such they do not have dependencies on the respective I/O power supply voltage. This allows external voltage sources to be connected to these I/O terminals when the respective I/O power supplies are turned off. The USB0_VBUS and USB1_VBUS are the only fail-safe I/O terminals. All other I/O terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the steady state max. Voltage at all I/O pins parameter in Section 5.1. (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 5.2 ESD Ratings VALUE UNIT VESD Electrostatic discharge (ESD) performance: Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001(1) ±2000 V Charged Device Model (CDM), per JESD22-C101(2) ±500 |
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