AM3359 datasheet(136/256 Pages) TI1

136 / 256 page

136

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

SPRS717L – OCTOBER 2011 – REVISED MARCH 2020

www.ti.com

Submit Documentation Feedback

Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

Peripheral Information and Timings

Table 7-27. GPMC and NOR Flash Timing Requirements—Asynchronous Mode

NO.

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

FA5(1)

tacc(d)

Data access time

H(5)

FA20(2)

tacc1-pgmode(d)

Page mode successive data access time

P(4)

FA21(3)

tacc2-pgmode(d)

Page mode first data access time

H(5)

(1) The FA5 parameter shows the amount of time required to internally sample input data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock

edge. FA5 value must be stored inside the AccessTime register bit field.

(2) The FA20 parameter shows amount of time required to internally sample successive input page data. It is expressed in number of

GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock

edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(3) The FA21 parameter shows amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by

active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

(4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)

(5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)

(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

Table 7-28. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

FA0

tw(be[x]nV)

Pulse duration, output lower-byte

enable and command latch enable

gpmc_be0n_cle, output upper-byte

enable gpmc_be1n valid time

Read

N(12)

Write

N(12)

FA1

tw(csnV)

Pulse duration, output chip select

gpmc_csn[x](13) low

Read

A(1)

Write

A(1)

FA3

td(csnV-advnIV)

Delay time, output chip select

gpmc_csn[x](13) valid to output

address valid and address latch

enable gpmc_advn_ale invalid

Read

B(2) – 0.2

B(2) + 2.0

B(2) – 5

B(2) + 5

Write

B(2) – 0.2

B(2) + 2.0

B(2) – 5

B(2) + 5

FA4

td(csnV-oenIV)

Delay time, output chip select gpmc_csn[x](13)

valid to output enable gpmc_oen invalid (Single

read)

C(3) – 0.2

C(3) + 2.0

C(3) – 5

C(3) + 5

FA9

td(aV-csnV)

Delay time, output address gpmc_a[27:1] valid

to output chip select gpmc_csn[x](13) valid

J(9) – 0.2

J(9) + 2.0

J(9) – 5

J(9) + 5

FA10

td(be[x]nV-csnV)

Delay time, output lower-byte enable and

command latch enable gpmc_be0n_cle, output

upper-byte enable gpmc_be1n valid to output

chip select gpmc_csn[x](13) valid

J(9) – 0.2

J(9) + 2.0

J(9) – 5

J(9) + 5

FA12

td(csnV-advnV)

Delay time, output chip select gpmc_csn[x](13)

valid to output address valid and address latch

enable gpmc_advn_ale valid

K(10) – 0.2

K(10) + 2.0

K(10) – 5

K(10) + 5

FA13

td(csnV-oenV)

Delay time, output chip select gpmc_csn[x](13)

valid to output enable gpmc_oen valid

L(11) – 0.2

L(11) + 2.0

L (11) – 5

L(11) + 5

FA16

tw(aIV)

Pulse durationm output address gpmc_a[26:1]

invalid between 2 successive read and write

accesses

G(7)

FA18

td(csnV-oenIV)

Delay time, output chip select gpmc_csn[x](13)

valid to output enable gpmc_oen invalid (Burst

read)

I(8) – 0.2

I(8) + 2.0

I(8) – 5

I(8) + 5

FA20

tw(aV)

Pulse duration, output address gpmc_a[27:1]

valid - 2nd, 3rd, and 4th accesses

D(4)

FA25

td(csnV-wenV)

Delay time, output chip select gpmc_csn[x](13)

valid to output write enable gpmc_wen valid

E(5) – 0.2

E(5) + 2.0

E(5) – 5

E(5) + 5

FA27

td(csnV-wenIV)

Delay time, output chip select gpmc_csn[x](13)

valid to output write enable gpmc_wen invalid

F(6) – 0.2

F(6) + 2.0

F(6) – 5

F(6) + 5

AM3359 Datasheet(PDF) 136 Page - Texas Instruments

AM3359 Datasheet(HTML) 136 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL