Figure 11. Application schematic

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Cann ot

VANA_2V8

\

o

e

p

p

e

m

n

-

f

s

i

t

l

.

e

st

AGND

AGND

DGND

DGND

DGND

DGND

VCORE_1V1

AGND

VANA_2V8

VANA_2V8

VANA_2V8

VDDIO_1V8

VDDIO_1V8

VDDIO_1V8

AGND

VCORE_1V1

VCORE_1V1

VCORE_1V1

DGND

PORTST

VANA_2V8

CPNEG

DGND

DATA2N

DATA2P

CLKN

CLKP

DATA1N

DATA1P

CSI2

CSI2

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

XSHUTDOWN

CLKIN

SDA

SCL

Host Interface

CLKIN

Host Interface

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

SDA

SCL

XSHUTDOWN

VDDIO_1V8

C_LDO2V4

AGND

VCORE_1V1

VANA_2V8

AGND

C_CPNEG

LDO2V4

VDDIO_1V8

DGND

C_VDDIO

DGND

C_VCORE

VCORE_1V1

VANA_2V8

AGND

C_VANA

Power supp ly decoup ling

C_CPPOS

AGND

CPPOS

VDDAMP

DGND

C_VDDAMP

AGND

DGND

6.2

Layout guidelines

For good PCB design practice, observe the following image sensor layout:

•

Use power and ground planes to supply power to the sensor.

•

Join grounds i.e. join AGND and DGND into one single, solid GND plane underneath the sensor.

•

Connect this GND plane to the sensor pins with one via per GND pin.

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To minimize risk of emissions, shield all vias and tracks attached to supplies by their respective GND nets.

•

Maximize copper fill on the power planes near the sensor and use vias to improve heat transfer from the

sensor. Consider including additional heatsinks close to the sensor if it is to be used at high temperatures.

•

Route the high-speed signal pairs of the MIPI CSI-2 interface with balanced and controlled impedance

differential traces (50 Ω single-ended impedance, 100 Ω differential impedance). This is a requirement for

high-speed signaling. Route each pair together and match them in length to target a maximum 10 ps skew.

VCPNEG_IN and VCPNEG_OUT must be connected together with a short track. The required decoupling

capacitor shall be placed on this path and not on an isolated track.

VCPPOS_IN and VCPPOS_OUT must be connected together with a short track. The required decoupling

capacitor shall be placed on this path and not on an isolated track.

VD66GY

Application schematic

DS13838 - Rev 7

page 20/37