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AD9102 Datasheet(PDF) 39 Page - Analog Devices |
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AD9102 Datasheet(HTML) 39 Page - Analog Devices |
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39 / 43 page  Data Sheet AD9102 REGISTER DESCRIPTIONS analog.com Rev. B | 39 of 43 DAC PATTERN REPEAT CYCLES REGISTER (DAC_PAT, ADDRESS 0X2B) Table 33. Bit Descriptions for DAC_PAT Bits Bit Name Settings Description Reset Access [15:8] RESERVED 0x01 RW [7:0] DAC_REPEAT_CYCLE The number of DAC pattern repeat cycles + 1, (0 → repeat 1 pattern). 0x01 RW TRIGGER START TO DOUT SIGNAL REGISTER (DOUT_START, ADDRESS 0X2C) Table 34. Bit Descriptions for DOUT_START Bits Bit Name Settings Description Reset Access [15:0] DOUT_START Time between Trigger low and DOUT signal high in number of DAC clock cycles. Increment = 1. 0x0003 RW 0x0003 3 DAC clock cycles (minimum). 0xFFFF 65535 DAC clock cycles (maximum). DOUT CONFIGURATION REGISTER (DOUT_CONFIG, ADDRESS 0X2D) Table 35. Bit Descriptions for DOUT_CONFIG Bits Bit Name Settings Description Reset Access [15:6] RESERVED 0x000 RW 5 DOUT_VAL Manually sets DOUT signal value; only valid when DOUT_MODE = 0 (manual mode). 0 RW 4 DOUT_MODE Set different enable signal mode. 0 RW 0 DOUT pin is output from SDO/SDI2/DOUT pin and is manually controlled by Bit 5 (DOUT_ENM) and Bit 10 (DOUT_EN) in Register 0x00, which must be set to use this feature. 1 DOUT pin is output from SDO/SDI2/DOUT. The pin is controlled by DOUT_START and DOUT_STOP fields. Bit 5 (DOUT_ENM) and Bit 10 (DOUT_EN) in Register 0x00 must be set to use this feature. [3:0] DOUT_STOP Time between pattern end and DOUT signal low in number of DAC clock cycles. Increment = 1. 0x0 RW 0x0 0 DAC clock cycles (minimum) 0xF 15 DAC clock cycles (maximum) DAC CONSTANT VALUE REGISTER (DAC_CST, ADDRESS 0X31) Table 36. Bit Descriptions for DAC_CST Bits Bit Name Settings Description Reset Access [15:4] DAC_CONST Most significant byte of DAC constant value 0x000 RW 0x7FF Digital constant = IOUTFS − 1 LSB 0x000 Digital constant = 0 0x800 Digital constant = −IOUTFS + 1 LSB [3:0] RESERVED 0x0 RW DAC DIGITAL GAIN REGISTER (DAC_DGAIN, ADDRESS 0X35) Table 37. Bit Descriptions for DAC_DGAIN Bits Bit Name Settings Description Reset Access [15:4] DAC_DIG_GAIN DAC digital gain. Range +2 to −2. 0x000 RW 0x400 Multiplies digital data at DAC channel path by +1 0x7FF Multiplies digital data at DAC channel path by +2 0x800 Multiplies digital data at DAC channel path by −2 0xC00 Multiplies digital data at DAC channel path by −1 |
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