AD9102 datasheet(29/43 Pages) AD

29 / 43 page

Data Sheet

AD9102

APPLICATIONS INFORMATION

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Rev. B | 29 of 43

SIGNAL GENERATION EXAMPLES

Figure 46 shows a waveform stored in the 4096 × 14-bit

SRAM in an address segment defined by the START_ADDR and

STOP_ADDR being output by the DAC. The waveform is repeated

once during each pattern period. In each pattern period, a start

delay is executed, then the pattern is read from SRAM.

Figure 46. Pattern in SRAM

Figure 47 shows a pulsed sine wave generated by the DAC. The

DDS generates a sine wave at a programmed frequency based

on Equation 8. The DAC input datapath is programmed with a

start delay and a number of sine wave cycles to output. Figure 48

shows a sawtooth wave shape generated by the DAC in successive

pattern periods with a start delay.

Figure 47. Pulsed Sine Wave in Pattern Periods

Figure 48. Pulsed Sawtooth Waveform in Pattern Periods

Figure 49 shows the DAC outputting a sine wave modulated by

an amplitude envelope. The sine wave is generated by the DDS,

and the amplitude envelope is stored in SRAM. A start delay

and a digital gain factor are applied in the DAC input data path.

Figure 50 and Figure 51 show the DAC generating continuous

waveforms—one with start delays, one without. Figure 52 shows an

FSK modulated signal generated using a list of DDS tuning word bit

fields stored in SRAM. The SRAM address counter is incremented

by the rising edge of the DDS output MSB.

Figure 49. DDS Output Amplitude Modulated by SRAM Envelope

Figure 50. Waveform with Start Delays

Figure 51. Waveform Without Start Delays

Figure 52. FSK Modulated Signal

AD9102 Datasheet(PDF) 29 Page - Analog Devices