AD9102 datasheet(20/43 Pages) AD

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Data Sheet

AD9102

THEORY OF OPERATION

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Rev. B | 20 of 43

Figure 1 is a block diagram of the AD9102. The AD9102 has a

single 14-bit current output DAC.

An on-chip band gap reference is provided. Optionally, an off-chip

voltage reference may be used. The full-scale DAC output current,

also known as gain, is governed by the current, IREF. IREF is the

current that flows through the IREF resistor. The IREF set resistor can

be on or off chip at the discretion of the user. When the on-chip

RSET resistor is in use, DAC gain accuracy can be improved by em-

ploying the built in automatic gain calibration capability. Automatic

calibration can be used with the on-chip reference or an external

REFIO voltage. See the Automatic IOUTFS Calibration section for a

procedure for automatic gain calibration.

The power supply rails for the AD9102 are AVDD for analog

circuits, CLKVDD/CLDO for the clock input receiver, and DVDD/

DLDO1/DLDO2 for the digital I/O and for the on-chip digital data-

path. AVDD, DVDD, and CLKVDD can range from 1.8 V to 3.3 V

nominal. DLDO1, DLDO2, and CLDO operate at 1.8 V. If DVDD =

1.8 V, DLDO1 and DLDO2 must be connected to DVDD, with the

on-chip LDOs disabled. All three supplies are provided externally in

this case. Also, if CLKVDD = 1.8 V, CLDO must be connected to

CLKVDD, with the on-chip LDO disabled.

Digital signals input to the 14-bit DAC are generated by on-chip

digital waveform generation resources. From a digital datapath,

14-bit samples are input to the DAC at the CLKP/CLKN sample

rate. The data path includes gain and offset corrections and a

digital waveform source selection multiplexer. Waveform sources

are SRAM, direct digital synthesizer (DDS), DDS output amplitude

modulated by SRAM data, a sawtooth generator, DC constant, and

a pseudorandom sequence generator.

The waveforms output by the source selection multiplexer have

programmable pattern characteristics. The waveforms can be set

up to be continuous pulsed (fixed pattern period and start delay

within each pattern period), or finite pulsed (a set number of pattern

periods are output, then the pattern stops). Pulsed waveforms

(finite or continuous) have a programmed pattern period and start

delay. The waveform is present in each pulse period following the

programmed pattern period start and the start delay.

A SPI port enables loading of data into SRAM and programming of

all the control registers inside the device.

SPI PORT

The AD9102 provides a flexible, synchronous serial communica-

tions (SPI) port that allows easy interfacing to application spe-

cific integrated circuits (ASICs), field-programmable gate arrays

(FPGAs), and industry-standard microcontrollers. The interface al-

lows read/write access to all registers that configure the AD9102

and to the on-chip SRAM. Its data rate can be up to the SCLK clock

speed shown in Table 3 and Table 4.

The SPI interface operates as a standard synchronous serial com-

munication port. Chip Select (CS) is an active low chip select pin.

When CS is active low, SPI address and data transfer begins on

the SCLK rising edge. The first bit coming on SDIO is a read/write

indicator (high for read, low for write). The next 15 bits are the initial

For multiple consecutive register write/read operations in the 0x00

to 0x60 address space, the SPI port automatically decrements the

writes to or reads from a set of contiguous addresses. Note that

0x60 must be used as the starting address for this to work. In this

mode, there is no provision to choose the beginning and ending

addresses to write. Refer to the SRAM section on how to access

the SRAM.

Table 12. Command Word

MSB

LSB

DB15

DB14

DB13

DB12

…

DB2

DB1

DB0

R/W

A14

A13

A12

…

When the first bit of the command byte is a logic low (R/W bit = 0),

the SPI command is a write operation. In this case, SDIO remains

an input (see Figure 29 and Figure 31). When the first bit of the

command byte is a logic high (R/W bit = 1), the SPI command is

a read operation. In this case, data is driven out of the SDIO (see

Figure 30).

The SPI interface has a provision for 4-wire (default) or 3-wire

interface set in Bit 14 (SPI3WIRE) and Bit 1 (SPI3WIREM) in

SPICONFIG (Register 0x00). In 4-wire SPI interface mode (see

Figure 31), the AD9102 acts as the responder, whereas the FPGA

(such as the SDP-K1) acts as the controller. Data is read from SDO

(Pin 7), and the data is written by the controller through SDIO (Pin

2). The SPI communication finishes after the CS pin goes high.

Figure 29. Serial Register Interface Timing, MSB First Write, 3-Wire SPI

Figure 30. Serial Register Interface Timing, MSB First Read, 3-Wire SPI

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