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AD1852

Rev. A | Page 14 of 20

The lowest two bits of the 16-bit serial control data word are

decoded as the address of the register into which the upper

14 bits are written. These bits are defined in Table 15.

Table 15. AD1852 Registers

Bit 1

Bit 0

Volume left

Volume right

Control register

VOLUME LEFT AND VOLUME RIGHT REGISTERS

A write operation to the left or right volume registers activates

the autoramp, clickless volume control feature of the AD1852.

The upper 10 bits of the volume control word increment or

decrement by 1 at a rate equal to the input sample rate. The

bottom four bits are not fed into the autoramp circuit and thus

take effect immediately. This arrangement gives a worst-case

ramp time of about 20 ms for step changes of more than 60 dB,

which was determined by listening tests to be optimal in terms of

preventing the perception of a click sound on large volume

changes. See Figure 28 for a graphical description of how the

volume changes as a function of time.

The 14-bit volume control word is used to multiply the signal,

and therefore, the control characteristic is linear, not dB. A

constant dB/step characteristic can be obtained by using a

lookup table in the microprocessor that is writing to the SPI

port. The volume word is unsigned (that is, 0 dB is 11 1111

1111 1111).

20ms

TIME

–60

VOLUME REQUEST REGISTER

ACTUAL VOLUME REGISTER

Figure 28. Smooth Volume Control

SPI TIMING

The SPI port is a 3-wire interface with serial data (CDATA),

serial bit clock (CCLK), and data latch (CLATCH). The data

is clocked into an internal shift register on the rising edge of

CCLK. The serial data should change on the falling edge of

CCLK and be stable on the rising edge of CCLK. The rising

edge of CLATCH is used internally to latch the parallel data

from the serial-to-parallel converter. This rising edge should be

aligned with the falling edge of the last CCLK pulse in the 16-bit

frame. The CCLK can run continuously between transactions.

Note that the serial control port timing is asynchronous to the

serial data port timing. Changes made to the attenuator level

update on the next edge of the LRCLK after the CLATCH write

pulse, as shown in Figure 27.

MUTE

The AD1852 offers two methods of muting the analog output.

By asserting the MUTE (Pin 23) signal high, both the left and

right channel are muted. As an alternative, the user can assert

the mute bit in the serial control register (Bit 6) high. The

AD1852 was designed to minimize pops and clicks when muting

and unmuting the device by automatically ramping the gain up

or down. When the device is unmuted, the volume returns to

the value set in the volume register.

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