DS3101 datasheet(49/149 Pages) DALLAS

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DS3101 Stratum 3/3E Timing Card IC

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7.9.1

Master-Slave Pin Feature

Some of the elements of redundancy configuration listed in Table 7-14 are automatically handled in the device

when the master-slave pin feature is used (MASTSLV). When this feature is supported in a system, one output

clock of the master device must be wired to input clock IC11 on the slave device, and one output clock of the slave

device should be wired to IC11 on the master device. This cross-wiring allows the system to dynamically configure

either device as master and the other as slave.

When the MASTSLV pin is wired low on one device, that device is configured as the slave. The other device must

be configured as the master by wiring its MASTSLV pin high. In each device the state of the MASTSLV pin is

always indicated in the read-only MASTSLV bit in register MCR3.

The slave device (MASTSLV = 0) is automatically configured as follows:

The priority of input clock IC11 is set to 1 (highest) (IPR6:PRI11[3:0] = 0001).

Phase build-out is disabled (MCR10:PBOEN = 0).

Revertive mode is enabled (MCR3:REVERT = 1).

T0 DPLL bandwidth is forced to the acquisition setting (i.e., to the setting in the T0ABW register,

which should be set to a high bandwidth by software).

In the master device (MASTSLV = 1), none of these settings are forced to specific values. Rather, each setting is

configured as needed for normal operation of the system. During configuration, software should configure the

master to disable (priority 0) input clock IC11 and should configure the remaining input clock priorities identically in

master and slave. During operation, software must maintain matching input clock priorities, as described in item 3

of Table 7-14.

The master-slave pin feature is optional and can be disabled by wiring the MASTSLV pin high on both devices. If

this feature is disabled, all the elements of equipment redundancy listed in Table 7-14 must be configured and

maintained by software.

7.9.2

Master-Slave Output Clock Phase Alignment

When the T0 DPLL is locked to a selected reference with frequency f, any output clocks derived from T0 with

frequency f are phase aligned with the selected reference (if phase build-out is disabled). Any output clocks derived

from T0 with frequency greater than f are “falling edge aligned” with the frequency-f output clock. Any output clocks

derived from T0 with frequency less than f may or may not be aligned, depending on whether or not their

frequencies are integer sub-multiples of f. These statements also apply to output clocks derived from the T4 DPLL.

Given this information, if master and slave devices are cross-wired with 19.44MHz clocks, for example, the output

clocks at N x 19.44MHz (N = 1, 2, 4, 8, or 16) from the two devices are phase-aligned with one another. Output

clocks at lower frequencies (6.48MHz, 1.544MHz, 2.048MHz, 2kHz, 8kHz, etc.) from the two devices would not

necessarily be phase aligned. In many systems, lack of phase alignment between the two devices at these clock

rates is not an issue. In some systems, however, the 2kHz and/or 8kHz clocks of the two devices must be aligned

to avoid framing errors during switchover between master and slave.

One way to align the 2kHz and/or 8kHz clocks of the master and slave devices is to configure the slave to lock to a

2kHz or 8kHz output of the master. Another way is to use the SYNC2K input as described in Section 7.9.3.

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