DS3101 datasheet(32/149 Pages) DALLAS

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DS3101 Stratum 3/3E Timing Card IC

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7.7.4

Damping Factor

The damping factor for the T0 DPLL is configured in the DAMP field of the T0CR2 register, while the damping

factor the T4 DPLL is configured in the DAMP field of the T4CR2 register. The reset default damping factors for

both DPLLs are chosen to give a maximum wander gain peak of approximately 0.1dB. Available settings are a

function of DPLL bandwidth (configured in the T4BW, T0ABW, and T0LBW registers). See Table 7-5.

Table 7-5. Damping Factors and Peak Jitter/Wander Gain

BANDWIDTH

DAMP[2:0]

VALUE

DAMPING FACTOR

GAIN PEAK (dB)

0.5mHz to 4Hz

1, 2, 3, 4, 5

0.1

2.5

0.2

8Hz

2, 3, 4, 5

0.1

1.2

0.4

2.5

0.2

18 Hz

3, 4, 5

0.1

1.2

0.4

2.5

0.2

0.1

35 Hz

4, 5

0.06

1.2

0.4

2.5

0.2

0.1

0.06

70 Hz

0.03

7.7.5

Phase Detectors

Phase detectors are used to compare a PLL’s feedback clock with its input clock. Several phase detectors are

available in both the T0 and T4 DPLLs:

Phase/frequency detector (PFD)

Early/late phase detector (PD2) for fine resolution

Multicycle phase detector (MCPD) for large input jitter tolerance

These detectors can be used in combination to give fine phase resolution combined with large jitter tolerance. As

with the rest of the DPLL logic, the phase detectors operate at input frequencies up to 77.76MHz. The multicycle

phase detector detects and remembers phase differences of many cycles (up to 8191UI).

The phase detectors can be configured for normal phase/frequency locking (

±360° capture) or nearest-edge phase

locking (

±180° capture). With nearest-edge detection the phase detectors are immune to occasional missing clock

cycles. The DPLL automatically switches to nearest-edge locking when the multicycle phase detector is disabled

and the other phase detectors determine that phase lock has been achieved. Setting D180 = 1 in the TEST1

The early/late phase detector, also known as phase detector 2, is enabled and configured in the PD2* fields of

registers T0CR2 and T0CR3 for the T0 DPLL and registers T4CR2 and T4CR3 for the T4 DPLL. The reset default

settings of these registers are appropriate for all operating modes. Adjustments only affect small signal overshoot

and bandwidth.

The multicycle phase detector is enabled by setting MCPDEN = 1 in the PHLIM2 register. The range of the

MCPD—from

±1UI up to ±8191UI—is configured in the COARSELIM field of PHLIM2. The MCPD tracks phase

position over many clock cycles, giving high jitter tolerance. Thus the use of the MCPD is an alternative to the use

of LOCK8K mode for jitter tolerance.

When USEMCPD = 1 in PHLIM2, the MCPD is used in the DPLL loop, giving faster pull-in but more overshoot. In

this mode the loop has similar behavior to LOCK8K mode. In both cases large phase differences contribute to the

dynamics of the loop. When enabled by MCPDEN = 1, the MCPD tracks the phase position whether or not it is

used in the DPLL loop.

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