DS3101 datasheet(18/149 Pages) DALLAS

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DS3101 Stratum 3/3E Timing Card IC

18 of 149

IA = analog input pin

OA = analog output pin (can be placed in a high-impedance state)

IPD = input pin with internal 50kΩ pulldown

O3 = output pin that can tri-stated (i.e., placed in a high-impedance state)

IPU = input pin with internal 50kΩ pullup to approx.2.2V

P = power-supply pin

I/O = input/output pin

Note 3:

All digital pins are I/O pins in JTAG mode.

Note 4:

When ramping power supplies up or down, the voltage on any 1.8V power supply pin must not exceed the voltage on any 3.3V power-

supply pin.

FUNCTIONAL DESCRIPTION

7.1

Overview

The DS3101 has 14 input clocks and 11 output clocks,. There are two separate DPLL paths in the device: the high-

performance T0 path and the simpler T4 path. See Figure 2-1.

Two of the 14 input clocks are 64kHz composite clock receivers (by default), two are LVDS/LVPECL, and 10 are

CMOS/TTL (5V tolerant). The composite clock receivers can be converted to CMOS/TTL inputs as needed. The

CMOS/TTL inputs can accept signals from 2kHz to 125MHz. The LVDS/LVPECL pins can accept clock signals up

to 155.52MHz.

Each input clock can be monitored continually for activity and/or frequency. Frequency can be compared to both a

hard limit and a soft limit. Inputs outside the hard limit are declared invalid, while inputs inside the hard limit but

outside the soft limit are merely flagged. Each input can be marked unavailable or given a priority number.

Separate input priority numbers are maintained for the T0 DPLL and the T4 DPLL. Except in special modes, the

highest priority valid input is automatically selected as the reference for each path.

Both the T0 and T4 DPLLs can directly lock to many common telecom frequencies, including, but not limited to

8kHz, DS1, E1, 19.44MHz, and 38.88MHz. The DPLLs can also lock to any multiple of 8kHz up to 125MHz.

The T0 DPLL is the high-performance path with all the features for node timing synchronization. The T4 DPLL is a

simpler auxiliary path typically used to provide derived DS1s, E1s, or other synchronization signals to an external

BITS/SSU. The two paths can be operated independently or locked together.

Both DPLLs have these features:

Automatic reference selection based on input quality and priority

Optional manual reference selection/forcing

Configurable quality thresholds for each input

Adjustable PLL characteristics, including bandwidth, pull-in range, and damping factor

Ability to lock to several common telecom frequencies plus multiples of 8kHz up to 155.52MHz

Frequency conversion between input and output using digital frequency synthesis

Combined performance of a stable, consistent digital PLL and a low-jitter analog output PLL

The T0 DPLL has these additional features not available in the T4 DPLL:

A full state machine for automatic transitions among free-run, locked, and holdover states

Nonrevertive reference switching mode

Phase build-out for reference switching (“hitless”) and for phase hits on the selected reference

Output vs. input phase offset control

18 bandwidth selections from 0.5mHz to 70Hz (vs. three selections for the T4 path)

Noise rejection circuitry for low-frequency references

Optional software control over holdover frequency

Output phase alignment to input frame sync signal

Several frequency averaging methods for acquiring the holdover frequency

The T4 DPLL has these additional features not available in the T0 DPLL:

Optional mode to lock to the T0 DPLL

DS3101 Datasheet(PDF) 18 Page - Dallas Semiconductor

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