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DS3101 Datasheet(PDF) 44 Page - Dallas Semiconductor

Part # DS3101
Description  Stratum 3/3E Timing Card IC
PDF  149 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3101 Datasheet(HTML) 44 Page - Dallas Semiconductor

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DS3101 Stratum 3/3E Timing Card IC
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Table 7-12. OC1 to OC7 Output Frequency Selection
FREQUENCY
REGISTER
VALUE
(1)
OC1
OC2
OC3
OC4
OC5
OC6
OC7
0000
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
0001
2kHz
2kHz
2kHz
2kHz
2kHz
2kHz
2kHz
0010
8kHz
8kHz
8kHz
8kHz
8kHz
8kHz
8kHz
0011
Digital2
Digital2
Digital2
Digital2
Digital2
T0 APLL/2
Digital2
0100
Digital1
Digital1
Digital1
Digital1
Digital1
Digital1
T0 APLL/2
0101
T0 APLL/48
T0 APLL/48
T0 APLL/48
T0 APLL/48
T0 APLL/48
T0 APLL/1
T0 APLL/48
0110
T0 APLL/16
T0 APLL/16
T0 APLL/16
T0 APLL/16
T0 APLL/16
T0 APLL/16
T0 APLL/16
0111
T0 APLL/12
T0 APLL/12
T0 APLL/12
T0 APLL/12
T0 APLL/12
T0 APLL/12
T0 APLL/12
1000
T0 APLL/8
T0 APLL/8
T0 APLL/8
T0 APLL/8
T0 APLL/8
T0 APLL/8
T0 APLL/8
1001
T0 APLL/6
T0 APLL/6
T0 APLL/6
T0 APLL/6
T0 APLL/6
T0 APLL/6
T0 APLL/6
1010
T0 APLL/4
T0 APLL/4
T0 APLL/4
T0 APLL/4
T0 APLL/4
T0 APLL/4
T0 APLL/4
1011
T4 APLL/64
T4 APLL/64
T4 APLL/64
T4 APLL/2
T4 APLL/2
T4 APLL/64
T4 APLL/64
1100
T4 APLL/48
T4 APLL/48
T4 APLL/48
T4 APLL/48
T4 APLL/48
T4 APLL/48
T4 APLL/48
1101
T4 APLL/16
T4 APLL/16
T4 APLL/16
T4 APLL/16
T4 APLL/16
T4 APLL/16
T4 APLL/16
1110
T4 APLL/8
T4 APLL/8
T4 APLL/8
T4 APLL/8
T4 APLL/8
T4 APLL/8
T4 APLL/8
1111
T4 APLL/4
T4 APLL/4
T4 APLL/4
T4 APLL/4
T4 APLL/4
T4 APLL/4
T4 APLL/4
Note 1: The value of the OFREQn field (in the OCR1 through OCR4 registers) corresponding to output clock OCn.
Table 7-13. Possible Frequencies for OC1 to OC7
JITTER (TYP)
FREQUENCY (MHz)
T0 DPLL MODE
T4 DPLL
MODE
T4 APLL
SOURCE
OFREQN
SETTING
RMS
(ps)
pk-pk
(ns)
2kHz
77.76MHz, analog
—
—
0001
60
0.6
2kHz
Any digital feedback
0001
1400
5.0
8kHz
77.76MHz, analog
0010
60
0.6
8kHz
Any digital feedback
0010
1400
5.0
1.536
Not OC4 or OC5
12 x E1
T4 DPLL
1011
55
0.6
1.536
Not OC4 or OC5
T0 12 x E1
1011
250
1.5
1.544
Via Digital1, not OC7
77.76MHz, analog
0100
3800
13
1.544
Via Digital2, not OC6
77.76MHz, analog
0011
3800
13
1.544
Via Digital1, not OC7
Any digital feedback
0100
3800
18
1.544
Via Digital2, not OC6
Any digital feedback
0011
3800
18
1.544
Not OC4 or OC5
16 x DS1
T4 DPLL
1011
140
1.2
1.544
Not OC4 or OC5
T0 16 x DS1
1011
275
1.9
1.578
Not OC4 or OC5
4 x 6312kHz
T4 DPLL
1011
240
1.5
1.578
Not OC4 or OC5
T0 4x6312kHz
1011
260
1.8
2.048
Not OC6
12 x E1 mode
0101
425
2.6
2.048
Via Digital1, not OC7
77.76MHz, analog
0100
3800
13
2.048
Via Digital2, not OC6
77.76MHz, analog
0011
3800
13
2.048
Via Digital1, not OC7
Any digital feedback
0100
3800
18
2.048
Via Digital2, not OC6
Any digital feedback
0011
3800
18
2.048
12 x E1
T4 DPLL
1100
55
0.6
2.048
T0 12 x E1
1100
250
1.5
2.048
Not OC4 or OC5
16 x E1
T4 DPLL
1011
50
0.5
2.048
Not OC4 or OC5
T0 16 x E1
1011
350
2.4
2.059
Not OC6
16 x DS1
0101
435
2.8
2.059
16 x DS1
T4 DPLL
1100
140
1.2
2.059
T0 16 x DS1
1100
275
1.9
2.104
Not OC6
4 x 6312 kHz
0101
340
2.3
2.104
4 x 6312kHz
T4 DPLL
1100
240
1.8
2.104
T0 4x6312kHz
1100
260
1.8
2.316
Not OC4 or OC5
24 x DS1
T4 DPLL
1011
150
1.0
2.316
Not OC4 or OC5
T0 24 x DS1
1011
400
2.8
2.731
Not OC6
16 x E1
0101
380
2.6
2.731
16 x E1
T4 DPLL
1100
50
0.5
2.731
T0 16 x E1
1100
350
2.4



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