DS3101 datasheet(3/149 Pages) DALLAS

3 / 149 page

DS3101 Stratum 3/3E Timing Card IC

3 of 149

7.8.2

Frequency Configuration .............................................................................................................. 39

7.9

EQUIPMENT REDUNDANCY CONFIGURATION .................................................................................48

7.9.1

Master-Slave Pin Feature............................................................................................................. 49

7.9.2

Master-Slave Output Clock Phase Alignment .............................................................................. 49

7.9.3

Master-Slave Frame and Multiframe Alignment with the SYNC2K Pin........................................ 50

7.10 COMPOSITE CLOCK RECEIVERS AND TRANSMITTER ......................................................................52

7.10.1 IC1 and IC2 Receivers ................................................................................................................. 53

7.10.2 OC8 Transmitter ........................................................................................................................... 53

7.11 MICROPROCESSOR INTERFACES ..................................................................................................55

7.11.1 Parallel Interface Modes............................................................................................................... 55

7.11.2 SPI Interface Mode....................................................................................................................... 55

7.12 RESET LOGIC ..............................................................................................................................57

7.13 POWER-SUPPLY CONSIDERATIONS ..............................................................................................58

7.14 INITIALIZATION .............................................................................................................................58

8. REGISTER DESCRIPTIONS ...............................................................................................59

8.1

STATUS BITS ...............................................................................................................................59

8.2

CONFIGURATION FIELDS ..............................................................................................................59

8.3

MULTIREGISTER FIELDS ...............................................................................................................59

8.4

REGISTER DEFINITIONS ...............................................................................................................60

9. JTAG TEST ACCESS PORT AND BOUNDARY SCAN....................................................125

9.1

JTAG DESCRIPTION ..................................................................................................................125

9.2

JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ...........................................................126

9.3

JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ....................................................................128

9.4

JTAG TEST REGISTERS ............................................................................................................129

10. ELECTRICAL CHARACTERISTICS..................................................................................130

10.1 DC CHARACTERISTICS ..............................................................................................................130

10.2 INPUT CLOCK TIMING .................................................................................................................134

10.3 OUTPUT CLOCK TIMING .............................................................................................................134

10.4 PARALLEL INTERFACE TIMING ....................................................................................................135

10.5 SPI INTERFACE TIMING..............................................................................................................138

10.6 JTAG INTERFACE TIMING ..........................................................................................................139

11. PIN ASSIGNMENTS ..........................................................................................................140

12. PACKAGE INFORMATION ...............................................................................................145

12.1 256-PIN CSBGA (17MM X 17MM) (56-G6017-001)....................................................................145

13. THERMAL INFORMATION ................................................................................................146

14. GLOSSARY .......................................................................................................................147

15. ACRONYMS AND ABBREVIATIONS ...............................................................................148

16. TRADEMARK ACKNOWLEDGEMENTS ..........................................................................148

17. DATA SHEET REVISION HISTORY..................................................................................149

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