DS3101 datasheet(2/149 Pages) DALLAS

2 / 149 page

DS3101 Stratum 3/3E Timing Card IC

2 of 149

TABLE OF CONTENTS

1. STANDARDS COMPLIANCE ................................................................................................6

2. BLOCK DIAGRAM.................................................................................................................7

3. APPLICATION EXAMPLE .....................................................................................................8

4. DETAILED DESCRIPTION ....................................................................................................8

5. DETAILED FEATURES .......................................................................................................10

5.1

T0 DPLL FEATURES....................................................................................................................10

5.2

T4 DPLL FEATURES....................................................................................................................10

5.3

INPUT CLOCK FEATURES .............................................................................................................10

5.4

OUTPUT CLOCK FEATURES ..........................................................................................................11

5.5

REDUNDANCY FEATURES.............................................................................................................11

5.6

COMPOSITE CLOCK I/O FEATURES...............................................................................................11

5.7

GENERAL FEATURES ...................................................................................................................11

6. PIN DESCRIPTIONS............................................................................................................12

7. FUNCTIONAL DESCRIPTION .............................................................................................18

7.1

OVERVIEW ..................................................................................................................................18

7.2

DEVICE IDENTIFICATION AND PROTECTION ...................................................................................19

7.3

LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION...........................................................19

7.4

INPUT CLOCK CONFIGURATION ....................................................................................................20

7.4.1

Signal Format Configuration......................................................................................................... 20

7.4.2

Frequency Configuration .............................................................................................................. 22

7.5

INPUT CLOCK QUALITY MONITORING ............................................................................................23

7.5.1

Frequency Monitoring................................................................................................................... 23

7.5.2

Activity Monitoring ........................................................................................................................ 23

7.5.3

Selected Reference Activity Monitoring ....................................................................................... 24

7.5.4

Composite Clock Inputs ............................................................................................................... 24

7.6

INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING ..................................................................25

7.6.1

Priority Configuration.................................................................................................................... 25

7.6.2

Automatic Selection Algorithm ..................................................................................................... 25

7.6.3

Forced Selection .......................................................................................................................... 26

7.6.4

Ultra-Fast Reference Switching.................................................................................................... 26

7.6.5

External Reference Switching Mode ............................................................................................ 26

7.6.6

Output Clock Phase Continuity During Reference Switching ...................................................... 27

7.7

DPLL ARCHITECTURE AND CONFIGURATION ................................................................................27

7.7.1

T0 DPLL State Machine ............................................................................................................... 27

7.7.2

T4 DPLL State Machine ............................................................................................................... 30

7.7.3

Bandwidth..................................................................................................................................... 31

7.7.4

Damping Factor ............................................................................................................................ 32

7.7.5

Phase Detectors........................................................................................................................... 32

7.7.6

Loss of Phase Lock Detection...................................................................................................... 33

7.7.7

Phase Monitor and Phase Build-Out............................................................................................ 34

7.7.8

Input to Output Phase Adjustment ............................................................................................... 35

7.7.9

Phase Recalibration ..................................................................................................................... 35

7.7.10 Frequency and Phase Measurement ........................................................................................... 35

7.7.11 Input Wander and Jitter Tolerance ............................................................................................... 36

7.7.12 Jitter and Wander Transfer........................................................................................................... 36

7.7.13 Output Jitter and Wander ............................................................................................................. 37

7.8

OUTPUT CLOCK CONFIGURATION.................................................................................................38

7.8.1

Signal Format Configuration......................................................................................................... 39

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