4571 datasheet(40/126 Pages) RENESAS

40 / 126 page

Rev.1.02

May 25, 2007

Page 40 of 124

REJ03B0179-0102

4571 Group

(2) Power-on reset

Reset can be automatically performed at power on (power-on

reset) by the built-in power-on reset circuit. When the built-in

power-on reset circuit is used, set the time for the supply voltage

to rise from 0 V to the minimum voltage of recommended

operating conditions to 100

µs or less.

If the rising time exceeds 100

µs, connect a capacitor between

the RESET pin and Vss at the shortest distance, and input “L”

level to RESET pin until the value of supply voltage reaches the

minimum operating voltage.

(3) System reset instruction (SRST)

By executing the SRST instruction, “L” level is output to RESET

pin and system reset is performed.

Fig 42. Power-on reset operation

Note 1.Output latch is set to “1.”

Note 2.The output structure is N-channel open-drain.

Note 3.Pull-up transistor is turned OFF.

100

µsor less

VDD (Note 1)

Power-on reset

circuit output

Internal reset signal

Note: Keep the value of supply voltage to

the minimum value or more of the

recommended operating conditions.

Reset

released

Reset

state

Power-on

Table 18 Port state at reset

Name

Function

State

−D3

High-impedance (Notes 1, 2)

D4/CNTR0

High-impedance (Note 1)

P00

−P03

P00

−P03

High-impedance (Notes 1, 3)

P10

−P13

P10

−P13

High-impedance (Notes 1, 3)

P20/INT0, P21/INT1

P20

, P21

High-impedance (Notes 1, 3)

P30, P31

High-impedance (Notes 1, 2)

C/CNTR1

(VSS)

High-impedance

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