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4571 Datasheet(PDF) 9 Page - Renesas Technology Corp |
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4571 Datasheet(HTML) 9 Page - Renesas Technology Corp |
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9 / 126 page ![]() Rev.1.02 May 25, 2007 Page 9 of 124 REJ03B0179-0102 4571 Group Fig 4. Port block diagram (2) Edge detection circuit Key-on wakeup input IAP1 instruction OP1A instruction (Note 1) (Note 1) P10 -P13(Note 2) D T Q K1i PU1i Ai Register A Ai (Note 3) (Note 3) (Note 4) (Note 3) Pull-up transistor IAP2 instruction OP2A instruction (Note 1) (Note 1) PU20 P20/INT0(Note 2) D T Q External 0 interrupt External 0 interrupt Key-on wakeup input Timer 1 count start synchronous circuit input (Notes 5, 6) A0 Register A A0 Edge detection circuit Key-on wakeup input K20 (Note 4) IAP2 instruction OP2A instruction (Note 1) (Note 1) PU21 P21/INT1(Note 2) D T Q External 1 interrupt External 1 interrupt Key-on wakeup input A1 Register A A1 Edge detection circuit Key-on wakeup input K21 (Note4) Pull-up transistor Pull-up transistor (Notes 5, 6) Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be V DD or less. 3. i represents bits 0 to 3. 4. Falling edge of port input is detected. 5. As for details, refer to the external interrupt structure. 6. The threshold value of port input is different from that of external interrupt input. |
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