4571 datasheet(67/126 Pages) RENESAS

67 / 126 page

Rev.1.02

May 25, 2007

Page 67 of 124

REJ03B0179-0102

4571 Group

INSTRUCTIONS

Each instruction is described as follows;

1. Index list of instruction function

2. Machine instructions (index by alphabet)

3. Machine instructions (index by function)

4. Instruction code table

The symbols shown below are used in the following list of

instruction function and the machine instructions.

Note 1.The 4571 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased

by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if

the TABP p, RT, or RTS instruction is skipped.

SYMBOL

Symbol

Contents

Symbol

Contents

T1F

Timer 1 interrupt request flag

T2F

Timer 2 interrupt request flag

T3F

Timer 3 interrupt request flag

WDF1

Watchdog timer flag

Interrupt control register V1 (4 bits)

WEF

Watchdog timer enable flag

Interrupt control register V2 (4 bits)

INTE

Interrupt enable flag

Interrupt control register I1 (4 bits)

EXF0

External 0 interrupt request flag

Interrupt control register I2 (4 bits)

EXF1

External 1 interrupt request flag

Timer control register PA (2 bits)

VDF

Voltage drop detection circuit interrupt request flag

Timer control register W1 (4 bits)

Power down flag

Timer control register W2 (4 bits)

Port D (5 bits)

Timer control register W3 (4 bits)

Port P0 (4 bits)

Timer control register W5 (4 bits)

Port P1 (4 bits)

Clock control register MR (4 bits)

Port P2 (2 bits)

Key-on wakeup control register K0 (4 bits)

Port P3 (2 bits)

Key-on wakeup control register K1 (4 bits)

Key-on wakeup control register K2 (4 bits)

Hexadecimal variable

Key-on wakeup control register L1 (4 bits)

Hexadecimal variable

PU0

Pull-up control register PU0 (4 bits)

Hexadecimal variable

PU1

Pull-up control register PU1 (4 bits)

Hexadecimal variable

PU2

Pull-up control register PU2 (4 bits)

Hexadecimal constant

FR0

Port output structure control register FR0 (4 bits)

Hexadecimal constant

FR1

Port output structure control register FR1 (4 bits)

Hexadecimal constant

A3 A2 A1 A0

Binary notation of hexadecimal variable A

(same for others)

Data pointer (10 bits)

(It consists of registers X, Y, and Z)

←

Direction of data movement

(

)

Contents of registers and memories

Program counter (14 bits)

−

Negate, Flag unchanged after executing instruction

PCH

High-order 7 bits of program counter

M (DP)

RAM address pointed by the data pointer

PCL

Low-order 7 bits of program counter

Label indicating address a6 a5 a4 a3 a2 a1 a0

Stack register (14 bits

× 8)

p, a

Label indicating address a6 a5 a4 a3 a2 a1 a0 in page

p6 p5 p4 p3 p2 p1 p0

Stack pointer (3 bits)

Carry flag

RPS

Prescaler reload register (8 bits)

Hex. C + Hex. number x (also same for others)

R1L

Timer 1 reload register (8 bits)

Timer 2 reload register (8 bits)

R3L

Timer 3 reload register (8 bits)

Decision of state shown before “?”

R3H

Timer 3 reload register (8 bits)

← →

Data exchange between a register and memory

Prescaler

Timer 1

AND

Logical multiplication

Timer 2

Logical addition

Timer 3

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