4571 datasheet(12/126 Pages) RENESAS

12 / 126 page

Rev.1.02

May 25, 2007

Page 12 of 124

REJ03B0179-0102

4571 Group

FUNCTION BLOCK OPERATIONS

CPU

(1) Arithmetic logic unit (ALU)

The arithmetic logic unit ALU performs 4-bit arithmetic such as

4-bit data addition, comparison, AND operation, OR operation,

and bit manipulation.

(2) Register A and carry flag

exchange, and I/O operation.

Carry flag CY is a 1-bit flag that is set to “1” when there is a

carry with the AMC instruction (Figure 7).

It is unchanged with both A n instruction and AM instruction.

The value of A0 is stored in carry flag CY with the RAR

instruction (Figure 8).

Carry flag CY can be set to “1” with the SC instruction and

cleared to “0” with the RC instruction.

(3) Registers B and E

data, and for 8-bit data transfer together with register A.

transfer with register B used as the high-order 4 bits and register

A as the low-order 4 bits (Figure 9).

returned from the RAM back-up. Accordingly, set the initial

value.

(4) Register D

It is used to store a 7-bit ROM address together with register A

and is used as a pointer within the specified page when the TABP

p, BLA p, or BMLA p instruction is executed (Figure 10).

Also, when the TABP p instruction is executed at UPTF flag =

“1”, the high-order 2 bits of ROM reference data is stored to the

low-order 2 bits of register D, the high-order 1 bit of register D is

“0”.

When the TABP p instruction is executed at UPTF flag = “0”, the

contents of register D remains unchanged. The UPTF flag is set

to “1” with the SUPT instruction and cleared to “0” with the

RUPT instruction.

The initial value of UPTF flag is “0”.

returned from the RAM back-up. Accordingly, set the initial

value.

Fig 7.

AMC instruction execution example

Fig 8.

RAR instruction execution example

Fig 9.

Registers A, B and register E

Fig 10. TABP p instruction execution example

(CY)

(M(DP))

(A)

Addition

ALU

<Carry>

<Clear>

RC instruction

<Set>

SC instruction

A3 A2 A1 A0

RAR instruction

CY A3 A2 A1

A3 A2 A1 A0

TAB instruction

E3 E2 E1 E0

E7 E6 E5 E4

B3 B2 B1 B0

TEAB instruction

A3 A2 A1 A0

TBA instruction

B3 B2 B1 B0

TABE instruction

A3 A2 A1 A0

DR2 DR1 DR0

PCL

Low-order 4bits

High-order 2 bits

Middle-order 4 bits

ROM

Immediate field

value p

The contents of

Specifying address

TABP p instruction

* Flag UPTF = 1;

High-order 2 bits of reference data is transferred to

the low-order 2 bits of register D.

“0” is stored to the high-order 1 bit of register D.

Flag UPTF = 0;

Data is not transferred to register D.

PCH

840

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