ADT7490 datasheet(67/76 Pages) AD

67 / 76 page

ADT7490

Rev. 0 | Page 67 of 76

Table 68. Register 0x74—Interrupt Mask Register 1 (Power-On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[0]

+2.5VIN/THERM

R/W

+2.5VIN/THERM = 1 masks SMBALERT for out-of-limit conditions on the +2.5VIN/THERM timer

channel.

[1]

VCCP

R/W

VCCP = 1 masks SMBALERT for out-of-limit conditions on the VCCP channel.

[2]

VCC

R/W

VCC = 1 masks SMBALERT for out-of-limit conditions on the VCC channel.

[3]

+5VIN

R/W

+5VIN = 1 masks SMBALERT for out-of-limit conditions on the +5VIN channel.

[4]

R1T

R/W

R1T = 1 masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.

[5]

R/W

LT = 1 masks SMBALERT for out-of-limit conditions on the Local temperature channel.

[6]

R2T

R/W

R2T = 1 masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.

[7]

OOL

R/W

OOL = 1 masks SMBALERT assertions when the OOL status bit is set.

Note that the OOL mask bit is independent of the individual mask bits associated with Interrupt

Status 2 register. Therefore, if the intention is to mask SMBALERT assertions for any of the Interrupt

Status 2 register bits, OOL must also be masked.

Table 69. Register 0x75—Interrupt Mask Register 2 (Power-On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[0]

+12VIN

R/W

When Pin 21 is configured as a +12VIN input, +12VIN = 1 masks SMBALERT for out-of-limit conditions

on the +12VIN channel.

[1]

OOL

R/W

OOL = 1 masks SMBALERT assertions when the OOL status bit is set.

Note that the OOL mask bit is independent of the individual mask bits in Interrupt Mask 3 register

(0x82). Therefore, if the intention is to mask SMBALERT assertions for any of the Status Register 4 bits,

OOL must also be masked.

[2]

FAN1

R/W

FAN1 = 1 masks SMBALERT for a Fan 1 fault.

[3]

FAN2

R/W

FAN2 = 1 masks SMBALERT for a Fan 2 fault.

[4]

FAN3

R/W

FAN3 = 1 masks SMBALERT for a Fan 3 fault.

[5]

F4P

R/W

If Pin 14 is configured as TACH4, F4P = 1 masks SMBALERT for a Fan 4 fault.

If Pin 14 is configured as THERM, F4P = 1 masks SMBALERT for an exceeded THERM timer limit.

[6]

R/W

D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel.

[7]

R/W

D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel.

Table 70. Register 0x76—Extended Resolution Register 1 (Power-On Default = 0x00)1

Bit No.

Mnemonic

R/W

Description

[1:0]

+2.5VIN

Read-only

+2.5VIN LSBs. Holds the 2 LSBs of the 10-bit +2.5VIN measurement.

[3:2]

VCCP

Read-only

VCCP LSBs. Holds the 2 LSBs of the 10-bit VCCP measurement.

[5:4]

VCC

Read-only

VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement.

[7:6]

+5VIN

Read-only

+5VIN LSBs. Holds the 2 LSBs of the 10-bit +5VIN measurement.

1 If this register is read, this register and the registers holding the MSB of each reading are frozen until read.

Table 71. Register 0x77—Extended Resolution Register 2 (Power-On Default = 0x00)1

Bit

Name

R/W

Description

[1:0]

+12VIN

Read-only

+12VIN LSBs. Holds the 2 LSBs of the 10-bit +12VIN measurement.

[3:2]

TDM1

Read-only

Remote 1 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement.

[5:4]

LTMP

Read-only

Local Temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement.

[7:6]

TDM2

Read-only

Remote 2 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement.

1 If this register is read, this register and the registers holding the MSB of each reading are frozen until read.

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