ADT7490 datasheet(71/76 Pages) AD

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ADT7490

Rev. 0 | Page 71 of 76

Table 78. Register 0x7E—Manufacturer’s Test Register 1 (Power-On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[7:0]

Reserved

Read-only

Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and

should not be written to under normal operation.

Table 79. Register 0x7F—Manufacturer’s Test Register 2 (Power-On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[7:0]

Reserved

Read-only

Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and

should not be written to under normal operation.

Table 80. Register 0x80—GPIO Configuration Register (Power-On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[1:0]

RES

Reserved

Reserved.

[2]

GPIO2

R/W

If GPIO2 is set to input, this register reflects the state of the pin. If GPIO2 is configured as an output,

writing to this register asserts the output high or low depending on the polarity.

[3]

GPIO1

R/W

If GPIO1 is set to input, this register reflects the state of the pin. If GPIO1 is configured as an output,

writing to this register asserts the output high or low depending on the polarity.

[4]

GPIO2 POL

R/W

GPIO2 polarity bit. Set to 0 for active low. Set to 1 for active high.

[5]

GPIO1 POL

R/W

GPIO1 polarity bit. Set to 0 for active low. Set to 1 for active high.

[6]

GPIO2 DIR

R/W

GPIO2 direction bit. Set to 1 for GPIO1 to act as an input, set to 0 for GPIO2 to act as an output.

[7]

GPIO1 DIR

R/W

GPIO1 direction bit. Set to 1 for GPIO1 to act as an input, set to 0 for GPIO1 to act as an output.

Table 81. Register 0x81—Interrupt Status Register 4 (Power-On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[2:0]

RES

Read-only

Reserved.

[3]

PECI1

Read-only

A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value from PECI Client

Address 0x31. This bit is cleared on a read of the status register only if the error condition has subsided.

[4]

PECI2

Read-only

A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value from PECI Client

Address 0x32. This bit is cleared on a read of the status register only if the error condition has subsided.

[5]

PECI3

Read-only

A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value from PECI Client

Address 0x33. This bit is cleared on a read of the status register only if the error condition has subsided.

[6]

IMON

Read-only

A Logic 1 indicates that the IMON high or low limit has been exceeded. This bit is cleared on a read of the

status register only if the error condition has subsided.

[7]

VTT

Read-only

A Logic 1 indicates that the VTT high or low limit has been exceeded. This bit is cleared on a read of the

status register only if the error condition has subsided.

Table 82. Register 0x82—Interrupt Mask Register 3 (Power-On Default = 0x00)1

Bit No.

Mnemonic

R/W

Description

[0]

PECI0

R/W

A Logic 1 masks SMBALERT assertions for out-of-limit conditions on PECI0.

[1]

DATA

R/W

A Logic 1 masks SMBALERT assertions for PECI data errors.

[2]

COMM

R/W

A Logic 1 masks SMBALERT assertions for PECI communications errors.

[3]

OVT

R/W

OVT = 1 masks SMBALERT for overtemperature THERM conditions.

[6:4]

RES

R/W

Reserved.

[7]

OOL

R/W

OOL = 1 masks SMBALERT assertions when the OOL status bit is set.

Note that the OOL mask bit is independent of the individual mask bits of Interrupt Mask 4 register

(0x83). Therefore, if the intention is to mask SMBALERT assertions for any of the Status Register 4 bits,

OOL must also be masked.

1 If the mask bits in Register 0x82 are set, it is also necessary to set the OOL mask bit in Register 0x75 to ensure the SMBALERT output is not asserted.

ADT7490 Datasheet(PDF) 71 Page - Analog Devices

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