ADT7490 datasheet(27/76 Pages) AD

27 / 76 page

ADT7490

Rev. 0 | Page 27 of 76

SMBALERT Interrupt Behavior

The ADT7490 can be polled for status, or an SMBALERT

interrupt can be generated for out-of-limit conditions. It is

important to note how the SMBALERT output and status

bits behave when writing interrupt handler software.

STICKY

STATUS BIT

HIGH LIMIT

TEMPERATURE

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

SMBALERT

Figure 31. SMBALERT and Status Bit Behavior

Figure 31 shows how the SMBALERT output and sticky status

bits behave. Once a limit is exceeded, the corresponding status

bit is set to 1. The status bit remains set until the error condi-

tion subsides and the status register is read. The status bits

are referred to as sticky, because they remain set until read

by software. This ensures that an out-of-limit event cannot

be missed if software is polling the device periodically.

Note that the SMBALERT output remains low for the entire

duration that a reading is out of limit and until the status

ware handles the interrupt.

Handling SMBALERT Interrupts

To prevent the system from being tied up servicing interrupts,

it is recommend to handle the SMBALERT interrupt as follows:

Detect the SMBALERT assertion.

Enter the interrupt handler.

Read the status registers to identify the interrupt source.

Mask the interrupt source by setting the appropriate mask

bit in the interrupt mask registers (0x74, 0x75, 0x82, and

0x83).

Take the appropriate action for a given interrupt source.

Exit the interrupt handler.

Periodically poll the status registers. If the interrupt status

bit has cleared, reset the corresponding interrupt mask bit

to 0. This causes the SMBALERT output and status bits to

behave as shown in Figure 32.

Masking Interrupt Sources

The interrupt mask registers allow individual interrupt sources

to be masked out to prevent SMBALERT interrupts. Note that

masking an interrupt source prevents only the SMBALERT

output from being asserted; the appropriate status bit is set

normally see Figure 32. Full details of the status and mask

registers associated with each measurement channel are

detailed in Table 20 and Table 24.

STICKY

STATUS BIT

HIGH LIMIT

TEMPERATURE

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

INTERRUPT

MASK BIT SET

SMBALERT

INTERRUPT MASK BIT

CLEARED

(SMBALERT REARMED)

Figure 32. How Masking the Interrupt Source Affects SMBALERT Output

Enabling the SMBALERT Interrupt Output

The SMBALERT interrupt function is disabled by default.

Pin 10 or Pin 14 can be reconfigured as an SMBALERT

output to signal out-of-limit conditions.

Table 21. Configuring Pin 10 as SMBALERT Output

Bit Setting

Configuration Register 3

(Register 0x78) Bit 0

[1] Pin 10 = SMBALERT

[0] Pin 10 = PWM2 (default)

Assigning THERM Functionality to a Pin

Pin 14 on the ADT7490 has three possible functions:

SMBALERT, THERM, and TACH4. The user chooses

the required functionality by setting Bit 0 and Bit 1 of

Configuration Register 4 at Address 0x7D.

If THERM is enabled (Bit 1, Configuration Register 3

at Address 0x78):

•

Pin 22 becomes THERM.

•

If Pin 14 is configured as THERM (Bit 0 and Bit 1 of

Configuration Register 4 at Address 0x7D), THERM is

enabled on this pin.

If THERM is not enabled:

•

Pin 22 becomes a 2.5 VIN measurement input.

•

If Pin 14 is configured as THERM, THERM is disabled on

this pin.

Table 22. Configuring Pin 14 in Register 0x7D

Bit 0

Bit 1

Function

TACH4

THERM

SMBALERT

Reserved

ADT7490 Datasheet(PDF) 27 Page - Analog Devices

ADT7490 Datasheet(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL