ADT7490 datasheet(72/76 Pages) AD

72 / 76 page

ADT7490

Rev. 0 | Page 72 of 76

Table 83. Register 0x83—Interrupt Mask Register 4 (Power-On Default = 0x00)1

Bit No.

Mnemonic

R/W

Description

[2:0]

RES

R/W

Reserved.

[3]

PECI1

R/W

A Logic 1 masks ALERT assertions for out-of-limit conditions on PECI1.

[4]

PECI2

R/W

A Logic 1 masks ALERT assertions for out-of-limit conditions on PECI2.

[5]

PECI3

R/W

A Logic 1 masks ALERT assertions for out-of-limit conditions on PECI3.

[6]

IMON

R/W

A Logic 1 masks ALERT assertions for out-of-limit conditions on IMON.

[7]

VTT

R/W

A Logic 1 masks ALERT assertions for out-of-limit conditions on VTT.

1 If the mask bits in Register 0x83 are set, it is also necessary to set the OOL mask bit in Register 0x82 to ensure the SMBALERT output is not asserted.

Table 84. VTT, IMON Limit Registers

R/W1

Description

Power-On Default

0x84

R/W

VTT Low Limit

0x00

0x85

R/W

IMON Low Limit

0x00

0x86

R/W

VTT High Limit

0xFF

0x87

R/W

IMON High Limit

0xFF

1 These registers becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.

Table 85. Register 0x88—PECI Configuration Register 2 (Power-On Default = 0x00)

Bit No.

Mnemonic

R/W1

Description

[2:0]

RES

R/W

Reserved.

[3]

DOM3

R/W

CPU Domain Count Information. Set to 0 indicates that CPU 4 associated with the PECI3 reading has a

single domain (default). Set to 1 indicates that the system CPU4 contains two domains.

[4]

DOM2

R/W

CPU Domain Count Information. Set to 0 indicates that CPU 3 associated with the PECI2 reading has a

single domain (default). Set to 1 indicates that the system CPU3 contains two domains.

[5]

DOM1

R/W

CPU Domain Count Information. Set to 0 indicates that CPU 2 associated with the PECI1 reading has a

single domain (default). Set to 1 indicates that the system CPU2 contains two domains.

[7:6]

#CPU

R/W

CPU Count. These bits indicate the number of CPUs in the system, which provide PECI thermal

information to the ADT7490.

00 = 1 CPU (default); indicates that PECI0 data is available from CPU 1 at Address 0x30.

01 = 2 CPUs; indicates that PECI0 data is available from CPU1 at Address 0x30 and PECI1 data is

available from CPU 2 at Address 0x31.

10 = 3 CPUs; indicates that PECI0 data is available from CPU1 at Address 0x30, PECI1 data is available

from CPU 2 at Address 0x31 and PECI2 data is available from CPU 3 at Address 0x32.

11 = 4 CPUs; indicates that PECI0 data is available from CPU1 at Address 0x30, PECI1 data is available

from CPU 2 at Address 0x31, PECI2 data is available from CPU 3 at Address 0x32 and PECI3 data is

available from CPU 4 at Address 0x33.

1 This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail.

Table 86. Operating Point Registers1, 2

R/W3

Description

Power-On Default

0x8A

R/W

PECI operating point register

0xFB

0x8B

R/W

Remote 1 operating point register (default = 100°C).

0x64

0x8C

R/W

Local temperature operating point register (default = 100°C).

0x64

0x8D

R/W

Remote 2 operating point register (default = 100°C).

0x64

1 These registers set the target operating point for each temperature channel when the dynamic TMIN control feature is enabled.

2 The fans being controlled are adjusted to maintain temperature about an operating point.

3 This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this register fail.

ADT7490 Datasheet(PDF) 72 Page - Analog Devices

ADT7490 Datasheet(HTML) 72 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL