LM51772 datasheet(42/112 Pages) TI

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8.3.13 Frequency Synchronization

The device features an internal phase looked loop (PLL), which is designed to transition the switching frequency

seamlessly between the frequency set by the RT pin and the external frequency synchronization signal. If

no external frequency is provided, the RT pin sets the center frequency of the synchronization range. The

external synchronization signal can change the switching frequency ±50%. To ensure low quiescent current,

the input buffer of the SYNC pin is disabled if no valid sync frequency, that is a frequency signal outside the

recommended synchronization range is applied.

The f(SW) synchronization stops if the device enters power save mode or μSleep operation, if enabled. Once the

converter enters the PWM operation again, the device re-syncs to a pin signal. The synchronization timings are

given in Figure 8-25

VT(SYNC)

OSC

PLL

CORE

LOGIC

SYNC

ACTIVITY

DETECTION

LIMITER

Figure 8-24. Main Oscillator Functional Block Diagram

V(SYNC)

VT+(SYNC)

PLL lock Cycles

VT-(SYNC)

td(Det,Sync)

RT pro gramed fsw

td(Det,Sync)

fsw Synced

RT pro gramed fsw

Figure 8-25. Timing Diagram SYNC Function

The SYNC pin can be programmed through I2C or configured via R2D interface:

• As input triggering on the rising edge

• As input triggering on the falling edge (180deg phase shift)

• As an output of the main oscillator clock

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LM51772 Datasheet(PDF) 42 Page - Texas Instruments