9 Layout

9.1 Layout Guidelines

Comparators are very sensitive to input noise. For best results, adhere to the following layout guidelines.

1. Use a printed-circuit-board (PCB) with a good, unbroken, low-inductance ground plane. Proper grounding

(use of a ground plane) helps maintain specified device performance.

Likewise, high performance board materials such as Rogers or high speed FR4 is also recommended.

2. Place a decoupling capacitor (100pF ceramic, surface-mount capacitor) between VCC and

VEE as close to the device as possible. Using multiple bypass capacitors in different decade ranges such as

100pF, 100nF, and 1µF provides the best noise reduction across frequency ranges.

3. On the inputs and the output, keep lead lengths as short and minimize capacitive coupling to the traces by

having a keepout area around the traces that is 3x the width of the traces. Also recommended is to keep

input traces away from the output traces.

4. Solder the device directly to the PCB rather than using a socket.

9.2 Layout Example

Figure 9-1. TLV3603-EP Layout Example

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TLV3603-EP

SNOSDK3 – SEPTEMBER 2024

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