PM7344 datasheet(232/293 Pages) PMC

232 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

216

TEST FEATURES DESCRIPTION

Simultaneously asserting the CSB, RDB and WRB inputs causes all output pins

and the data bus to be held in a high-impedance state. This test feature may be

used for board testing.

Test mode registers are used to apply test vectors during production testing of

the S/UNI-MPH. Test mode registers (as opposed to normal mode registers) are

mapped into addresses 400H-7FFH.

Test mode registers may also be used for board testing. When all of the

constituent Telecom System Blocks within the S/UNI-MPH are placed in test

mode 0, device inputs may be read and device outputs may be forced via the

microprocessor interface (refer to the section "Test Mode 0" for details).

Notes on Test Mode Register Bits:

1. Writing values into unused register bits has no effect. Reading unused bits

can produce either a logic 1 or a logic 0; hence unused register bits should be

masked off by software when read.

2. Writeable test mode register bits are not initialized upon reset unless

otherwise noted.

PM7344 Datasheet(PDF) 232 Page - PMC-Sierra, Inc