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PM7344 Datasheet(PDF) 274 Page - PMC-Sierra, Inc |
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PM7344 Datasheet(HTML) 274 Page - PMC-Sierra, Inc |
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274 / 293 page  PM7344 S/UNI-MPH DATA SHEET PMC-950449 ISSUE 6 MULTI-PHY USER NETWORK INTERFACE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 258 Figure 39 - Microprocessor Write Access Timing tH DW Valid Data D[7:0] tVWR tSAW tHAW tS DW (CSB+WRB) A[10:0] Valid Address ALE tVL tSALW tSLW tHALW tHLW Notes on Microprocessor Interface Write Timing: 1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2. Microprocessor Interface timing applies to normal mode register accesses only. 3. In non-multiplexed address/data bus architectures, ALE can be held high, parameters tSALW, tHALW, tVL, tSLW, and tHLW are not applicable. 4. Parameters tHAW and tSAW are not applicable if address latching is used. 5. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. |
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