PM7344 datasheet(273/293 Pages) PMC

273 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

257

4. Microprocessor Interface timing applies to normal mode register accesses

only.

5. When a set-up time is specified between an input and a clock, the set-up

time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4

Volt point of the clock.

6. When a hold time is specified between an input and a clock, the hold time is

the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt

point of the input.

7. In non-multiplexed address/data bus architectures ALE can be held high;

parameters tSALR, tHALR, tVL, tSLR, and tHLR are not applicable.

8. Parameter tHAR is not applicable when address latching is used.

Table 7

- Microprocessor Write Access (Figure 39)

Symbol

Parameter

Min

Max

Units

tSAW

Address to Valid Write Set-up Time

tSDW

Data to Valid Write Set-up Time

tSALW

Address to Latch Set-up Time

tHALW

Address to Latch Hold Time

tVL

Valid Latch Pulse Width

tSLW

Latch to Write Set-up

tHLW

Latch to Write Hold

tHDW

Data to Valid Write Hold Time

tHAW

Address to Valid Write Hold Time

tVWR

Valid Write Pulse Width

PM7344 Datasheet(PDF) 273 Page - PMC-Sierra, Inc

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