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PM7344 Datasheet(PDF) 123 Page - PMC-Sierra, Inc |
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PM7344 Datasheet(HTML) 123 Page - PMC-Sierra, Inc |
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123 / 293 page  PM7344 S/UNI-MPH DATA SHEET PMC-950449 ISSUE 6 MULTI-PHY USER NETWORK INTERFACE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 107 Registers 01AH, 11AH, 21AH and 31AH: DJAT Output Clock Divisor (N2) Control Bit Type Function Default Bit 7 R/W N2[7] 0 Bit 6 R/W N2[6] 0 Bit 5 R/W N2[5] 1 Bit 4 R/W N2[4] 0 Bit 3 R/W N2[3] 1 Bit 2 R/W N2[2] 1 Bit 1 R/W N2[1] 1 Bit 0 R/W N2[0] 1 These registers define an 8-bit binary number, N2, which is one less than the magnitude of the divisor used to scale down the DJAT smooth output clock signal. The output clock divisor magnitude, (N2+1), is the ratio between the frequency of the smooth output clock and the frequency applied to the phase discriminator input. Writing to this register will reset the PLL and, if the SYNC bit is high, will also reset the FIFO. |
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