PM7344 datasheet(125/293 Pages) PMC

125 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

109

SYNC:

The SYNC bit enables the PLL to synchronize the phase delay between the

FIFO input and output data to the phase delay between reference clock input

and smooth output clock at the PLL. For example, if the PLL is operating so

that the smooth output clock lags the reference clock by 24 UI, then the

synchronization pulses that the PLL sends to the FIFO will force its output

data to lag its input data by 24 UI. If the SYNC bit is set to 1, the Clock

Divisors (Registers x19H and x1AH) must be set such that N1+1 and N2+1 is

a multiple of 48.

LIMIT:

The LIMIT bit enables the PLL to limit the jitter attenuation by enabling the

FIFO to increase or decrease the frequency of the smooth output clock

whenever the FIFO is within one unit interval (UI) of overflowing or

underflowing. This limiting of jitter ensures that no data is lost during high

phase shift conditions. When LIMIT is set to logic 1, the PLL jitter attenuation

is limited. When LIMIT is set to logic 0, the PLL is allowed to operate

normally.

PM7344 Datasheet(PDF) 125 Page - PMC-Sierra, Inc