PM7344 datasheet(129/293 Pages) PMC

129 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

113

When BEEE is set to logic 0, bit error events are disabled from generating an

interrupt.

SFEE:

The SFEE bit enables the generation of an interrupt when a severely errored

framing event has been detected. A severely errored framing event is defined

as 2 or more framing bit errors during the current superframe for SF and ESF

formatted data. When SFEE is set to logic 1, the detection of a severely

errored framing event is allowed to generate an interrupt. When SFEE is set

to logic 0, severely errored framing events are disabled from generating an

interrupt.

MFPE:

The MFPE bit enables the generation of an interrupt when the frame find

circuitry detects the presence of framing bit mimics. The occurrence of a

mimic is defined as more than one framing bit candidate following the frame

alignment pattern. When MFPE is set to logic 1, the assertion or deassertion

of the detection of a mimic is allowed to generate an interrupt. When MFPE is

set to logic 0, the detection of a mimic framing pattern is disabled from

generating an interrupt.

INFRE:

The INFRE bit enables the generation of an interrupt when the frame find

circuitry changes state. When INFRE is set to logic 1, the assertion or

deassertion of the "inframe" state is allowed to generate an interrupt. When

INFRE is set to logic 0, a change in the "inframe" state is disabled from

generating an interrupt.

PM7344 Datasheet(PDF) 129 Page - PMC-Sierra, Inc