PM7344 datasheet(133/293 Pages) PMC

133 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

117

A logic 1 in the CHKSEQ bit position enables the use of the check sequence

algorithm in addition to the basic frame find algorithms; a logic 0 disables the

use of the check sequence algorithm.

REFR:

A transition from logic 0 to logic 1 in the REFR bit position forces the re-

synchronization to a new frame alignment. The bit must be cleared to logic 0,

then set to logic 1 again to generate subsequent re-synchronizations.

REFCRCE:

The REFCRCE bit enables excessive CRC errors (≥ 915 errors in one

second) to force a re-synchronization to a new frame alignment. Setting the

REFCRCE bit position to logic 1 enables reframe due to excessive CRC

errors; setting the REFCRCE bit to logic 0 disables CRC errors from causing

a reframe.

REFRDIS:

The REFRDIS bit disables reframing under any error condition once frame

alignment has been found; reframing can be initiated by software via the

REFR bit. A logic 1 in the REFRDIS bit position causes the E1-FRMR to

remain "locked in frame" once initial frame alignment has been found. A logic

0 allows reframing to occur based on the various error criteria (FER,

excessive CRC errors, etc).

PM7344 Datasheet(PDF) 133 Page - PMC-Sierra, Inc