PM7344 datasheet(128/293 Pages) PMC

128 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

112

Registers 01DH, 11DH, 21DH and 31DH: T1-FRMR Interrupt Enable

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

R/W

Reserved

Bit 5

R/W

COFAE

Bit 4

R/W

FERE

Bit 3

R/W

BEEE

Bit 2

R/W

SFEE

Bit 1

R/W

MFPE

Bit 0

R/W

INFRE

These registers select which of the MFP, COFA, FER, BEE, SFE, or INFR events

generates an interrupt on the microprocessor INTB pin when their state changes

or their event condition is detected.

Reserved:

The reserved bit must be programmed to logic 0 for correct operation.

COFAE:

The COFAE bit enables the generation of an interrupt when the frame find

circuitry determines that frame alignment has been achieved and that the

new alignment differs from the previous alignment. When COFAE is set to

logic 1, the declaration of a change of frame alignment is allowed to generate

an interrupt. When COFAE is set to logic 0, a change in the frame alignment

does not generate an interrupt.

FERE:

The FERE bit enables the generation of an interrupt when a framing bit error

has been detected. When FERE is set to logic 1, the detection of a framing

bit error is allowed to generate an interrupt. When FERE is set to logic 0, any

error in the framing bits does not generate an interrupt.

BEEE:

The BEEE bit enables the generation of an interrupt when a bit error event

has been detected. A bit error event is defined as framing bit errors for SF

formatted data, and CRC-6 errors for ESF formatted data. When BEEE is set

to logic 1, the detection of a bit error event is allowed to generate an interrupt.

PM7344 Datasheet(PDF) 128 Page - PMC-Sierra, Inc

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