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PM7364 FREEDM-32

DATA SHEET

PMC-1960758

ISSUE 6

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

DESCRIPTION

The PM7364 FREEDM-32 Frame Engine and Datalink Manager device is a

monolithic integrated circuit that implements HDLC processing, and PCI Bus

memory management functions for a maximum of 128 bi-directional channels.

For channelised links, the FREEDM-32 allows up to 128 bi-directional HDLC

channels to be assigned to individual time-slots within a maximum of 32

independently timed T1 or E1 links. The channel assignment supports the

concatenation of time-slots (N x DS0) up to a maximum of 24 concatenated time-

slots for a T1 link and 31 concatenated time-slots for an E1 link. Time-slots

assigned to any particular channel need not be contiguous within the T1 or E1

link.

For unchannelised links, the FREEDM-32 processes up to 32 bi-directional

HDLC channels within 32 independently timed links. The links can be of

arbitrary frame format. When limited to two unchannelised links, each link can

be rated at up to 45 MHz when SYSCLK is at 25 MHz and at up to 52 MHz when

SYSCLK is at 33 MHz. For lower rate unchannelised links, the FREEDM-32

processes up to 32 links, where the aggregate clock rate of all the links is limited

to 64 MHz, links 0 to 2 can have a clock rate of up to 45 MHz when SYSCLK is

at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz and links 3 to

31 can have a clock rate of up to 10 MHz.

The FREEDM-32 supports mixing of up to 32 channelised and unchannelised

links. The total number of channels in each direction is limited to 128. The

aggregate clock rate over all 32 possible links is limited to 64 MHz.

In the receive direction, the FREEDM-32 performs channel assignment and

packet extraction and validation. For each provisioned HDLC channel, the

FREEDM-32 delineates the packet boundaries using flag sequence detection,

and performs bit de-stuffing. Sharing of opening and closing flags, as well as,

sharing of zeros between flags are supported. The resulting packet data is

placed into the internal 8 kbyte partial packet buffer RAM. The partial packet

buffer acts as a logical FIFO for each of the assigned channels. Partial packets

are DMA'd out of the RAM, across the PCI bus and into host packet memory.

The FREEDM-32 validates the frame check sequence for each packet, and

verifies that the packet is an integral number of octets in length and is within a

programmable minimum and maximum length. The receive packet status is

updated before linking the packet into a receive ready queue. The FREEDM-32

alerts the PCI Host that there are packets in a receive ready queue by, optionally,

asserting an interrupt on the PCI bus.

PM7364 Datasheet(PDF) 21 Page - PMC-Sierra, Inc

PM7364 Datasheet(HTML) 21 Page - PMC-Sierra, Inc

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