PM7364 datasheet(11/325 Pages) PMC

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RELEASED

PM7364 FREEDM-32

DATA SHEET

PMC-1960758

ISSUE 6

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

LIST OF FIGURES

FIGURE 1 – HDLC FRAME...............................................................................31

FIGURE 2 – CRC GENERATOR.......................................................................32

FIGURE 3 – PARTIAL PACKET BUFFER STRUCTURE ..................................36

FIGURE 4 – RECEIVE PACKET DESCRIPTOR...............................................38

FIGURE 5 – RECEIVE PACKET DESCRIPTOR TABLE...................................41

FIGURE 6 – RPDRF AND RPDRR QUEUES ...................................................43

FIGURE 7 – RPDRR QUEUE OPERATION......................................................45

FIGURE 8 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.........46

FIGURE 9 – GPIC ADDRESS MAP ..................................................................53

FIGURE 10 – TRANSMIT DESCRIPTOR .........................................................55

FIGURE 11 – TRANSMIT DESCRIPTOR TABLE .............................................59

FIGURE 12 – TDRR AND TDRF QUEUES .......................................................61

FIGURE 13 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE ....63

FIGURE 14 – TD LINKING................................................................................66

FIGURE 15 – PARTIAL PACKET BUFFER STRUCTURE ................................70

FIGURE 16 – INPUT OBSERVATION CELL (IN_CELL) .................................275

FIGURE 17 – OUTPUT CELL (OUT_CELL) ...................................................276

FIGURE 18 – BI-DIRECTIONAL CELL (IO_CELL) .........................................276

FIGURE 19 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS

..............................................................................................................277

FIGURE 20 – BOUNDARY SCAN ARCHITECTURE ......................................279

FIGURE 21 – TAP CONTROLLER FINITE STATE MACHINE........................281

FIGURE 22 – UNCHANNELISED RECEIVE LINK TIMING ............................285

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