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PM7364 Datasheet(PDF) 12 Page - PMC-Sierra, Inc |
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PM7364 Datasheet(HTML) 12 Page - PMC-Sierra, Inc |
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12 / 325 page ![]() RELEASED PM7364 FREEDM-32 DATA SHEET PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE xi FIGURE 23 – CHANNELISED T1 RECEIVE LINK TIMING ............................286 FIGURE 24 – CHANNELISED E1 RECEIVE LINK TIMING ............................286 FIGURE 25 – UNCHANNELISED TRANSMIT LINK TIMING..........................287 FIGURE 26 – CHANNELISED T1 TRANSMIT LINK TIMING..........................287 FIGURE 27 – CHANNELISED E1 TRANSMIT LINK TIMING .........................288 FIGURE 28 – PCI READ CYCLE ....................................................................289 FIGURE 29 – PCI WRITE CYCLE ..................................................................291 FIGURE 30 – PCI TARGET DISCONNECT ....................................................292 FIGURE 31 – PCI TARGET ABORT................................................................292 FIGURE 32 – PCI BUS REQUEST CYCLE ....................................................293 FIGURE 33 – PCI INITIATOR ABORT TERMINATION ...................................294 FIGURE 34 – PCI EXCLUSIVE LOCK CYCLE ...............................................295 FIGURE 35 – PCI FAST BACK TO BACK.......................................................297 FIGURE 36 – RECEIVE BERT PORT TIMING ...............................................297 FIGURE 37 – TRANSMIT BERT PORT TIMING .............................................298 FIGURE 38 – RECEIVE LINK INPUT TIMING ................................................303 FIGURE 39 – BERT INPUT TIMING ...............................................................303 FIGURE 40 – TRANSMIT LINK OUTPUT TIMING..........................................305 FIGURE 41 – BERT OUTPUT TIMING ...........................................................305 FIGURE 42 – PCI INTERFACE TIMING .........................................................306 FIGURE 43 – JTAG PORT INTERFACE TIMING............................................307 FIGURE 44 – 256 PIN ENHANCED BALL GRID ARRAY (SBGA) ..................309 |
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