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PM7367 Datasheet(PDF) 24 Page - PMC-Sierra, Inc

Part # PM7367
Description  FRAME ENGINE AND DATA LINK MANAGER
PDF  323 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7367 Datasheet(HTML) 24 Page - PMC-Sierra, Inc

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PM7367 FREEDM-32P32
DATA SHEET
PMC-1991499
ISSUE 2
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
10
Pin Name
Type
Pin
No.
Function
RD[0]
RD[1]
RD[2]
RD[3]
RD[4]
RD[5]
RD[6]
RD[7]
RD[8]
RD[9]
RD[10]
RD[11]
RD[12]
RD[13]
RD[14]
RD[15]
RD[16]
RD[17]
RD[18]
RD[19]
RD[20]
RD[21]
RD[22]
RD[23]
RD[24]
RD[25]
RD[26]
RD[27]
RD[28]
RD[29]
RD[30]
RD[31]
Input
H3
G2
F1
G4
E1
E3
E4
D5
C5
B5
D7
B6
A6
A7
B8
D9
B9
D10
B10
A11
B11
B12
D12
B13
A14
C14
B15
C15
B16
A17
U16
V16
The receive data signals (RD[31:0]) contain
the recovered line data for the 32
independently timed links in normal mode
(PMCTEST set low). Processing of the
receive links is on a priority basis, in
descending order form RD[0] to RD[31].
Therefore, the highest rate link should be
connected to RD[0] and the lowest to
RD[31].
For channelised links, RD[n] contains the 24
(T1) or 31 (E1) time-slots that comprise the
channelised link. RCLK[n] must be gapped
during the T1 framing bit position or the E1
frame alignment signal (time-slot 0). The
FREEDM-32P32 uses the location of the
gap to determine the channel alignment on
RD[n].
For unchannelised links, RD[n] contains the
HDLC packet data. For certain transmission
formats, RD[n] may contain place holder bits
or time-slots. RCLK[n] must be externally
gapped during the place holder positions in
the RD[n] stream. The FREEDM-32P32
supports a maximum data rate of 10 Mbit/s
on an individual RD[31:3] link and a
maximum data rate of 52 Mbit/s on RD[2:0].
RD[31:0] is sampled on the rising edge of
the corresponding RCLK[31:0] clock.
RBD
Tristate
Output
H1
The receive BERT data signal (RBD)
contains the receive bit error rate test data.
RBD reports the data on the selected one of
the receive data signals (RD[31:0]) and is
updated on the falling edge of RBCLK.
RBD may be tri-stated by setting the RBEN
bit in the FREEDM-32P32 Master BERT
Control register low.



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