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PM7367 Datasheet(PDF) 100 Page - PMC-Sierra, Inc |
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PM7367 Datasheet(HTML) 100 Page - PMC-Sierra, Inc |
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100 / 323 page ![]() PM7367 FREEDM-32P32 DATA SHEET PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 86 Register 0x008 : FREEDM-32P32 Master Interrupt Status Bit Type Function Default Bit 31 to Bit 16 Unused XXXXH Bit 15 R TFUDRI X Bit 14 R IOCI X Bit 13 R TDFQEI X Bit 12 R TDQRDYI X Bit 11 R TDQFI X Bit 10 R RPDRQEI X Bit 9 R RPDFQEI X Bit 8 R RPQRDYI X Bit 7 R RPQLFI X Bit 6 R RPQSFI X Bit 5 R RFOVRI X Bit 4 R RPFEI X Bit 3 R RABRTI X Bit 2 R RFCSEI X Bit 1 R PERRI X Bit 0 R SERRI X This register reports the interrupt status for various events detected or initiated by the FREEDM. Reading this registers acknowledges and clears the interrupts. Note This register is not byte addressable. Reading this register clears all the interrupt bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. |
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