PM7367 datasheet(101/323 Pages) PMC

101 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

SERRI:

The system error interrupt status bit (SERRI) reports PCI system error

interrupts to the PCI host. SERRI is set high upon detection of any address

parity error, data parity error on Special Cycle commands, reception of a

master abort or detection of a target abort event. The SERRI bit remains

valid when interrupts are disabled and may be polled to detect PCI system

error events.

PERRI:

The parity error interrupt status bit (PERRI) reports PCI parity error interrupts

to the PCI host. PERRI is set high when data parity errors are detected by

the FREEDM-32P32 while acting as a master, and when parity errors are

reported to the FREEDM-32P32 by a target via the PERRB input. The

PERRI bit remains valid when interrupts are disabled and may be polled to

detect PCI parity error events.

RFCSEI:

The receive frame check sequence error interrupt status bit (RFCSEI) reports

receive FCS error interrupts to the PCI host. RFCSEI is set high, when a

mismatch between the received FCS code and the computed CRC residue is

detected. RFCSEI remains valid when interrupts are disabled and may be

polled to detect receive FCS error events.

RABRTI:

The receive abort interrupt status bit (RABRTI) reports receive HDLC abort

interrupts to the PCI host. RABRTI is set high upon receipt of an abort code

(at least 7 contiguous 1's). RABRTI remains valid when interrupts are

disabled and may be polled to detect receive abort events.

RPFEI:

The receive packet format error interrupt status bit (RPFEI) reports receive

packet format error interrupts to the PCI host. RPFEI is set high upon receipt

of a packet that is longer than the maximum programmed length, of a packet

that is shorter than 32 bits (CRC-CCITT) or 48 bits (CRC-32), or of a packet

that is not octet aligned. RPFEI remains valid when interrupts are disabled

and may be polled to detect receive packet format error events.

RFOVRI:

The receive FIFO overrun error interrupt status bit (RFOVRI) reports receive

FIFO overrun error interrupts to the PCI host. RFOVRI is set high on

attempts to write data into the logical FIFO of a channel when it is already full.

RFOVRI remains valid when interrupts are disabled and may be polled to

detect receive FIFO overrun events.

PM7367 Datasheet(PDF) 101 Page - PMC-Sierra, Inc

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