PM7367 datasheet(64/323 Pages) PMC

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PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

8.5.2 Master Local Bus Interface

The master local bus is a 32 bit data bus which connects the local master device

to the GPIC. The GPIC contains two local master interface blocks, with one

supporting the RMAC and the other the TMAC. Each local master interface has

been optimised to support the traffic pattern generated by the RMAC or the

TMAC and are not interchangeable.

The data path between the GPIC and local master device provides a mechanism

to segregate the system timing domain of the core from the PCI bus. Transfers

on each of the RMAC and TMAC interfaces are timed to its own system clock.

The DMA controllers isolated from all aspects of the PCI bus protocol, and

instead “sees” a simple synchronous protocol. Read or write cycles on the local

master bus will initiate a request for service to the GPIC which will then transfer

the data via the PCI bus.

The GPIC maximises data throughput between the PCI bus and the local device

by paralleling local bus data transfers with PCI access latency. The GPIC allows

either DMA controller to write data independent of each other and independent of

PCI bus control. The GPIC temporarily buffers the data from each DMA

controller while it is arbitrating for control of the PCI bus. After completion of a

write transfer, the DMA controller is then released to perform other tasks. The

GPIC can buffer only a single transaction from each DMA controller.

Read accesses on the local bus are optimised by allowing the DMA controllers

access to the data from the PCI bus as soon as the first data becomes available.

After the initial synchronisation and PCI bus latency data is transferred at the

slower of PCI bus rate or the core logic SYSCLK rate. Once a read transaction

is started, the DMA controller is held waiting for the ready signal while the GPIC

is arbitrating for the PCI bus.

All data is passed between the GPIC and the DMA controllers in little Endian

format and, in the default mode of operation, the GPIC expects all data on the

PCI bus to also be in little Endian format. The GPIC provides a selection bit in

the internal Control register which allows the Endian format of the PCI bus data

to be changed. If enabled, the GPIC will swizzle all packet data on the PCI bus

(but not descriptor references and the contents of descriptors). The swizzling is

performed according to the “byte address invariance” rule, i.e. the only change

to the data is the mirror-imaging of byte lanes.

The interface for the RMAC provides for byte addressability of write transactions

whereas the interface for the TMAC provides for byte addressability of read

transactions. Other transactions must be dword aligned. For byte-addressable

transactions, the data transferred between the local device and the GPIC need

not be dword aligned with the data as it is presented on the PCI bus. The GPIC

PM7367 Datasheet(PDF) 64 Page - PMC-Sierra, Inc

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