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PM7367 Datasheet(PDF) 94 Page - PMC-Sierra, Inc |
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PM7367 Datasheet(HTML) 94 Page - PMC-Sierra, Inc |
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94 / 323 page  PM7367 FREEDM-32P32 DATA SHEET PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 80 the PCI Interface is held in reset. This bit is not self-clearing. Therefore, a logic zero must be written to bring the FREEDM-32P32 out of reset. Holding the FREEDM-32P32 in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset. Note Unlike the hardware reset input (RSTB), RESET does not force the FREEDM- 32's PCI pins tri-state. Transmit link data pins (TD[31:0]) are forced high. In addition, all registers except the GPIC PCI Configuration registers, are reset to their default values. |
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