PM7367 datasheet(271/323 Pages) PMC

271 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

257

Bit

Type

Function

Default

Bit 31

Bit 24

Reserved

00H

Bit 23

MLTFNC

Bit 22

Bit 16

HDTYPE[6:0]

00H

Bit 15

Bit 8

R/W

LT[7:0]

00H

Bit 7

Bit 0

R/W

CLSIZE

00H

CLSIZE[7:0]:

The Cache Line Size (CLSIZE[7:0]) bits specify the size of the system

cacheline in units of dwords. The GPIC uses this value to determine the type

of read command to issue in a Master Read transfer. If the transfer size is

equal to one, the GPIC will issue a Memory Read command. If the transfer

size is equal to or less than the CLSIZE, the GPIC will issue a Memory Read

Line command. For transfers larger than CLSIZE, the GPIC issues a

Memory Read Multiple command.

LT[7:0]:

The Latency Timer (LT[7:0]) bits specify in units of the PCI clock, the value of

the Latency Timer for the GPIC. At reset the value is zero.

HDTYPE[6:0]:

The Header Type (HDTYPE[6:0]) bits specify the layout of the base address

registers. Only the 00H encoding is supported.

MLTFNC:

The Multi-Function (MLTFNC) bit specifies if the GPIC supports multiple PCI

functions. If this bit is set low, the device only supports one function and if the

bit is set high, the device supports multi-functions. The MLTFNC bit is set low

to indicate the GPIC only supports one PCI function.

PM7367 Datasheet(PDF) 271 Page - PMC-Sierra, Inc

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