PM7367 datasheet(303/323 Pages) PMC

303 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

289

agent is driving the signals for this clock cycle). This cycle on the PCI bus is

called the address phase.

During clock 2, the initiator ceases to drive the address onto the AD[31:0] bus

and starts driving the first data word. The initiator also drives the C/BEB[3:0]

lines with the byte enables for the write data. IRDYB is driven active by the

initiator to indicate it is ready to accept the data transfer. The target claims the

transaction by driving DEVSELB active and drives TRDYB to indicate to the

initiator that it is ready to accept the data. All subsequent cycles on the PCI bus

are called data phases.

During clock 3, the target latches in the first data word. The initiator starts to

drive the next data word onto the AD[31:0] lines.

During clock 4, the target latches in the second data word. Both the initiator and

the target indicate that they are not ready to transfer any more data by negating

the ready lines.

During clock 5, the initiator is ready to transfer the next data word so it drives the

AD[31:0] lines with the third data word and asserts IRDYB. The initiator negates

FRAMEB since this is the last data phase of this cycle. The target is still not

ready so a wait state shall be added.

During clock 6, the target is still not ready so another wait state is added.

During clock 7, the target asserts TRDYB to indicate that it is ready to complete

the transfer.

During clock 8, the target latches in the last word and negates TRDYB and

DEVSELB, having seen FRAMEB negated previously. The initiator negates

IRDYB. All of the above signals shall be driven to their inactive state in this clock

cycle except for FRAMEB which shall be tri-stated.

PM7367 Datasheet(PDF) 303 Page - PMC-Sierra, Inc