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PM7367 Datasheet(PDF) 308 Page - PMC-Sierra, Inc

Part # PM7367
Description  FRAME ENGINE AND DATA LINK MANAGER
PDF  323 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7367 Datasheet(HTML) 308 Page - PMC-Sierra, Inc

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PM7367 FREEDM-32P32
DATA SHEET
PMC-1991499
ISSUE 2
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
294
Figure 34 – PCI Exclusive Lock Cycle
PCICLK
FRAMEB
AD[31:0]
1
2
3
4
5
678
9
TRDYB
DEVSELB
T
Address
Data
T
IRDYB
T
T
T
LOCKB
T
T
T
Address
Data
T
T
T
Fast back-to-back transactions are used by an initiator to conduct two
consecutive transactions on the PCI bus without the required idle cycle between
them. This can only occur if there is a guarantee that there will be no contention
between the initiator or targets involved in the two transactions. In the first case,
an initiator may perform fast back-to-back transactions if the first transaction is a
write and the second transaction is to the same target. All targets must be able
to decode the above transaction. In the second case, all of the targets on the
PCI bus support fast back-to-back transactions, as indicated in the PCI Status
configuration register. The FREEDM-32P32 only supports the first type of fast
back-to-back transactions and is shown in Figure 35.
During clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also
drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with
the write command. In this example the command would indicate a single write.
The IRDYB, TRDYB and DEVSELB signals are in turnaround mode and are not
being driven for this clock cycle. This cycle on the PCI bus is called the address
phase.
During clock 2, the initiator ceases to drive the address onto the AD[31:0] bus
and starts driving the data element. The initiator also drives the C/BEB[3:0] lines
with the byte enables for the write data. IRDYB is driven active by the initiator to
indicate that the data is valid.
The initiator negates FRAMEB since this the last data phase of this cycle. The
target claims the transaction by driving DEVSELB active and drives TRDYB to
indicate to the initiator that it is ready to accept the data.



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