PM7367 datasheet(128/323 Pages) PMC

128 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

114

FTHRES[6:0]:

The framing bit threshold bits (FTHRES[6:0]) contains the threshold used by

the clock activity monitor to detect for the presence of framing bits. A counter

in the clock activity monitor of each receive link increments at each SYSCLK

and is cleared, when the BSYNC bit of that link is set low, by each rising edge

of the corresponding RCLK[n]. When the BSYNC bit of that link is set high,

the counter is cleared at every fourth rising edge of the corresponding

RCLK[n]. When the counter exceeds the threshold given by FTHRES[6:0], a

framing bit/byte has been detected. FTHRES[6:0] should be set as a function

of the SYSCLK period and the expected gapping width of RCLK[n] during

data bits and during framing bits/bytes. Legal range of FTHRESH[6:0] is

'b0000001 to 'b1111110.

Note: For operation with T1 links and SYSCLK = 33 MHz, FTHRESH[6:0]

should be set to ‘b0011111’. The default value of this register is inconsistent

with that of the TCAS Framing Bit Threshold register 0x408.

PM7367 Datasheet(PDF) 128 Page - PMC-Sierra, Inc